SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 851

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
36.6.2.2
6500C–ATARM–8-Feb-11
Comparator
The comparator continuously compares its counter value with the channel period defined by
CPRD in the
defined by CDTY in the
generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
• the clock selection. The channel counter is clocked by one of the clocks provided by the
• the waveform period. This channel parameter is defined in the CPRD field of the
• the waveform duty-cycle. This channel parameter is defined in the CDTY field of the
clock generator described in the previous section. This channel parameter is defined in the
CPRE field of the
reset at 0.
PWM_CPRDx register.
If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1,
2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
X CPRD
CRPD DIVA
2 X CPRD
2 CPRD
duty cycle
×
×
×
duty cycle
MCK
MCK
MCK
×
MCK
×
“PWM Channel Period Register” on page 920
)
×
DIVA
=
)
)
=
(
------------------------------------------------------------------------------------------------------- -
or
period 1 fchannel_x_clock
(
---------------------------------------------------------------------------------------------------------------------- -
)
(
“PWM Channel Mode Register” on page 916
period 2 ⁄
or
(
----------------------------------------- -
CRPD DIVB
“PWM Channel Duty Cycle Register” on page 918
(
--------------------------------------------------- -
2
MCK
×
×
CPRD
) 1 fchannel_x_clock
MCK
period
×
)
(
period 2 ⁄
DIVB
)
)
×
CDTY
×
CDTY
)
(PWM_CPRDx) and the duty-cycle
) )
(PWM_CMRx). This field is
(PWM_CDTYx) to
SAM3S
851

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