SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 865

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6500C–ATARM–8-Feb-11
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatic update by setting the field
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC transfer request must be set in
5. Define the PDC transfer settings for the duty-cycle values and enable it in the PDC
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write regis-
8. Set UPDULOCK to 1 in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At
10. If an update of the update period value is required, check first that write of a new update
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous chan-
13. Check the end of the PDC transfer by the flag ENDTX. If the transfer has ended, define
UPDM to 2 in the PWM_SCM register.
the update period by the PTRM bit and the PTRCS field in the PWM_SCM register (at
the end of the update period or when a comparison matches).
registers
ters that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to
this moment the bit UPDULOCK is reset, go to
value is possible by polling the flag WRDY (or by waiting for the corresponding inter-
rupt) in the PWM_ISR2 register, else go to
nels when the Update Period is elapsed. Go to
a new PDC transfer in the PDC registers for new duty-cycle values. Go to
Step 13.
Step 7.
Step 10.
for new values.
for new values.
Step 5.
SAM3S
Step 10.
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