SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 867

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.6.3
6500C–ATARM–8-Feb-11
PWM Comparison Units
The PWM provides 8 independent comparison units able to compare a programmed value with
the current value of the channel 0 counter (which is the channel counter of all synchronous
channels,
erate pulses on the event lines (used to synchronize ADC, see
Lines”), to generate software interrupts and to trigger PDC transfer requests for the synchronous
channels (see
update” on page
Figure 36-14. Comparison Unit Block Diagram
The comparison x matches when it is enabled by the bit CEN in the
Register”
the comparison value defined by the field CV in
(PWM_CMPxV for the comparison x). If the counter of the channel 0 is center aligned (CALG =
1 in
is made when the counter is counting up or counting down (in left alignment mode CALG=0, this
bit is useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see
36.6.2.6 “Fault
The user can define the periodicity of the comparison x by the fields CTR and CPR (in
PWM_CMPxV). The comparison is performed periodically once every CPR+1 periods of the
counter of the channel 0, when the value of the comparison period counter CPRCNT (in
PWM_CMPxM) reaches the value defined by CTR. CPR is the maximum value of the compari-
son period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the
counter of the channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the
“PWM Comparison x Mode Update Register”
x). In the same way, the comparison x value can be modified while the channel 0 is enabled by
using the
comparison x).
“PWM Channel Mode Register”
“PWM Comparison x Value Update Register”
Section 36.6.2.7 “Synchronous
(PWM_CMPxM for the comparison x) and when the counter of the channel 0 reaches
CEN [PWM_CMPxM]
fault on channel 0
CV [PWM_CMPxV]
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CVM [PWM_CMPxV]
CALG [PWM_CMR0]
CPRCNT [PWM_CMPxM]
CTR [PWM_CMPxM]
Protection”).
“Method 3: Automatic write of duty-cycle values and automatic trigger of the
864).
), the bit CVM (in PWM_CMPxV) defines if the comparison
Channels”). These comparisons are intended to gen-
=
=
=
(PWM_CMPxMUPD registers for the comparison
1
0
1
“PWM Comparison x Value Register”
(PWM_CMPxVUPD registers for the
Section 36.6.4 “PWM Event
“PWM Comparison x Mode
Comparison x
SAM3S
Section
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