SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 868

no-image

SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 36-15. Comparison Waveform
868
Comparison Update
Comparison Match
SAM3S
CVMVUPD
CUPRUPD
CUPRCNT
CPRUPD
CTRUPD
CPRCNT
CVUPD
CCNT0
CMPM
CMPU
CUPR
CVM
CPR
CTR
CV
0x6
0x1
0x1
0x3
0x6
0x1
0x1
0x3
0x0
0x0
The update of the comparison x configuration and the comparison x value is triggered periodi-
cally after the comparison x update period. It is defined by the field CUPR in the PWM_CMPxM.
The comparison unit has an update period counter independent from the period counter to trig-
ger this update. When the value of the comparison update period counter CUPRCNT (in
PWM_CMPxM) reaches the value defined by CUPR, the update is triggered. The comparison x
update period CUPR itself can be updated while the channel 0 is enabled by using the
PWM_CMPxMUPD register.
CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be fol-
lowed by a write of the register PWM_CMPxMUPD.
The comparison match and the comparison update can be source of an interrupt, but only if it is
enabled and not masked. These interrupts can be enabled by the
ter 2”
and the comparison update interrupt are reset by reading
and disabled by the
0x1
0x1
0x2
0x2
0x0
0x2
0x3
0x2
0x3
0x1
“PWM Interrupt Disable Register 2”
0x2
0x2
0x2
0x0
0x0
0x3
0x1
0x1
0x2
0x2
0x0
0x3
0x6
the“PWM Interrupt Status Register 2”
0x1
0x0
. The comparison match interrupt
0x2
0x1
“PWM Interrupt Enable Regis-
0x6
0x0
0x2
6500C–ATARM–8-Feb-11
0x1
0x3
.

Related parts for SAM3S4B