SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 876

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.6.5.7
876
SAM3S
Write Protect Registers
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the field WPCMD in the
on page 909
There are two types of Write Protect:
Both types of Write Protect can be applied independently to a particular register group by means
of the WPCMD and WPRG fields in PWM_WPCR register. If at least one Write Protect is active,
the register group is write-protected. The field WPCMD allows to perform the following actions
depending on its value:
At any time, the user can determine which Write Protect is active in which register group by the
fields WPSWS and WPHWS in the
(PWM_WPSR).
If a write access in a write-protected register is detected, then the WPVS flag in the
PWM_WPSR register is set and the field WPVSRC indicates in which register the write access
has been attempted, through its address offset without the two LSBs.
The WPVS and PWM_WPSR fields are automatically reset after reading the PWM_WPSR
register.
• Register group 0:
• Register group 1:
• Register group 2:
• Register group 3:
• Register group 4:
• Register group 5:
• Write Protect SW, which can be enabled or disabled.
• Write Protect HW, which can just be enabled, only a hardware reset of the PWM controller
• 0 = Disabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
• 1 = Enabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
• 2 = Enabling the Write Protect HW of the register groups of which the bit WPRG is at 1.
can disable it.
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“PWM Clock Register” on page 880
“PWM Disable Register” on page 882
“PWM Sync Channels Mode Register” on page 888
“PWM Channel Mode Register” on page 916
“PWM Stepper Motor Mode Register” on page 908
“PWM Channel Period Register” on page 920
“PWM Channel Period Update Register” on page 921
“PWM Channel Dead Time Register” on page 923
“PWM Channel Dead Time Update Register” on page 924
“PWM Fault Mode Register” on page 902
“PWM Fault Protection Value Register” on page 905
(PWM_WPCR). They are divided into 6 groups:
“PWM Write Protect Status Register” on page 911
“PWM Write Protect Control Register”
6500C–ATARM–8-Feb-11