SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 921

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.7.40
Name:
Addresses:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
6500C–ATARM–8-Feb-11
911.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
31
23
15
–
7
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
(
--------------------------------------------
(
----------------------------------------------------- -
(
---------------------------------------------------------------- -
(
------------------------------------------------------- -
X CPRDUPD
2 X CPRDUPD
2 CPRDUPD DIVA
CRPDUPD
PWM Channel Period Update Register
×
×
×
MCK
×
MCK
MCK
MCK
×
30
22
14
DIVA
PWM_CPRDUPDx [x=0..3]
0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
–
6
)
Write-only
×
)
)
or
)
(
------------------------------------------------------- -
or
CRPDUPD DIVB
(
---------------------------------------------------------------- -
2 CPRDUPD
29
21
13
–
5
×
MCK
×
MCK
×
)
DIVB
28
20
12
–
4
CPRDUPD
CPRDUPD
CPRDUPD
)
27
19
11
–
3
“PWM Write Protect Status Register” on
26
18
10
–
2
25
17
–
9
1
SAM3S
24
16
–
8
0
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