SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 97

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.12.6
10.12.6.1
10.12.6.2
6500C–ATARM–8-Feb-11
LDM and STM
Syntax
Operation
Load and Store Multiple registers.
where:
op
addr_mode
cond
Rn
!
reglist
contain register ranges. It must be comma separated if it contains more than one register or reg-
ister range, see
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full
Descending stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending
stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto
Empty Ascending stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending
stacks
LDM instructions load the registers in reglist with word values from memory addresses based on
Rn.
STM instructions store the word values in the registers in reglist to memory addresses based on
Rn.
For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the
accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of reg-
isters in reglist. The accesses happens in order of increasing register numbers, with the lowest
numbered register using the lowest memory address and the highest number register using the
highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written
back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at
4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist.
op{addr_mode}{cond} Rn{!}, reglist
LDM
STM
IA
DB
If ! is present the final address, that is loaded from or stored to, is written back into Rn.
is one of:
Load Multiple registers.
Store Multiple registers.
is any one of the following:
Increment address After each access. This is the default.
Decrement address Before each access.
is an optional condition code, see
is the register on which the memory addresses are based.
is an optional writeback suffix.
is a list of one or more registers to be loaded or stored, enclosed in braces. It can
“Examples” on page
98.
“Conditional execution” on page
84.
SAM3S
97