SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 489
SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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28.14.11 PMC Master Clock Register
Name:
Address:
Access:
• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• UPLLDIV: UPLL Divider
0: UPLLDIV = 1 (clock is not divided).
1: UPLLDIV = 2 (clock is divided by 2).
UPLLDIV must be set (clock divided by 2) when UPLL is selected as source of clock for MCK or PCK.
6430E–ATARM–29-Aug-11
31
23
15
–
–
–
7
–
Value
Value
0
1
2
3
0
1
2
3
4
5
6
7
PMC_MCKR
0x400E0430
Read-write
30
22
14
–
–
–
6
Name
SLOW_CLK
MAIN_CLK
PLLA_CLK
UPLL_CLK
Name
UPLLDIV
PRES
CLK_16
CLK_32
CLK_64
CLK_1
CLK_2
CLK_4
CLK_8
CLK_3
29
21
13
–
–
5
28
20
12
–
–
–
4
Description
Slow Clock is selected
Main Clock is selected
PLLA Clock is selected
UPLL/2 Clock is selected
Description
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Selected clock divided by 3
27
19
11
–
–
–
3
–
26
18
10
–
–
–
–
2
SAM3U Series
25
17
–
–
–
9
1
CSS
24
16
–
–
–
8
0
489
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