SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 836
SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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37.11.1
37.11.2
37.12 HSMCI Transfer Done Timings
37.12.1
37.12.2
836
836
SAM3U Series
SAM3U Series
Boot Procedure, Processor Mode
Boot Procedure DMA Mode
Definition
Read Access
The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is
finished.
During a read access, the XFRDONE flag behaves as shown in
1. Configure the HSMCI data bus width programming SDCBUS Field in the
2. Set the byte count to 512 bytes and the block count to the desired number of blocks,
3. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register
4. The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the
5. Host processor can copy boot data sequentially as soon as the RXRDY flag is
6. When Data transfer is completed, host processor shall terminate the boot stream by
1. Configure the HSMCI data bus width by programming SDCBUS Field in the
2. Set the byte count to 512 bytes and the block count to the desired number of blocks by
3. Enable DMA transfer in the HSMCI_DMA register.
4. Configure DMA controller, program the total amount of data to be transferred and
5. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register
6. DMA controller copies the boot partition to the memory.
7. When DMA transfer is completed, host processor shall terminate the boot stream by
HSMCI_SDCR register. The BOOT_BUS_WIDTH field located in the device Extended
CSD register must be set accordingly.
writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
BOOT_ACK field of the MMC device located in the Extended CSD register is set to one.
asserted.
writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
HSMCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD
register must be set accordingly.
writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
enable the relevant channel.
with SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
Figure
37-11.
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
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