SAM7S161 Atmel Corporation, SAM7S161 Datasheet - Page 114
SAM7S161
Manufacturer Part Number
SAM7S161
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S161
Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Coprocessor Interface
4.4.6
4.4.7
4-10
Execute stage
Decode stage
coprocessor)
coprocessor)
Fetch stage
(from ARM)
Coprocessor data operations
Coprocessor load and store operations
CPA (from
CPB (from
D[31:0]
MCLK
nCPI
Coprocessor data operations, CDP instructions, perform processing operations on the
data held in the coprocessor register bank. No information is transferred between the
ARM7TDMI processor and the coprocessor as a result of this operation. An example
sequence is shown in Figure 4-3.
The coprocessor load and store instructions are used to transfer data between a
coprocessor and memory. They can be used to transfer either a single word of data, or
a number of the coprocessor registers. There is no limit to the number of words of data
that can be transferred by a single LDC or STC instruction, but by convention no more
than 16 words should be transferred in a single instruction. An example sequence is
shown in Figure 4-4 on page 4-11.
If you transfer more than 16 words of data in a single instruction, the worst case
interrupt latency of the ARM7TDMI processor increases.
ADD
Instr fetch
(ADD)
Note
Copyright © 1994-2001. All rights reserved.
ADD
SUB
Instr fetch
(SUB)
MCR
SUB
ADD
Instr fetch
(MCR)
Figure 4-3 Coprocessor data operation sequence
MCR
SUB
TST
Instr fetch
(TST)
MCR
SUB
TST
Instr fetch
(SUB)
SUB
TST
Instr fetch
ARM DDI 0029G
SUB
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