SAM7SE32 Atmel Corporation, SAM7SE32 Datasheet - Page 78
SAM7SE32
Manufacturer Part Number
SAM7SE32
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE32
Flash (kbytes)
32 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Interface
3.3.4
3-8
Merged IS cycles
Where possible the ARM7TDMI processor broadcasts the address for the next access,
so that decode can start, but the memory controller must not commit to a memory
access. This is shown in Figure 3-4 and, is further described in Nonsequential memory
cycle on page 3-6.
Where possible, the ARM7TDMI processor performs an optimization on the bus to
allow extra time for memory decode. When this happens, the address of the next
memory cycle is broadcast on this bus during an internal cycle. This enables the
memory controller to decode the address, but it must not initiate a memory access
during this cycle. In a merged IS cycle, the next cycle is a sequential cycle to the same
memory location. This commits to the access, and the memory controller must initiate
the memory access. This is shown in Figure 3-5 on page 3-9.
Copyright © 1994-2001. All rights reserved.
nMREQ
D[31:0]
A[31:0]
MCLK
nRAS
nCAS
SEQ
N-cycle
a
a+4
S-cycle
Figure 3-4 Internal cycles
a+8
I-cycle
ARM DDI 0029G
a+12
C-cycle
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