SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 250
SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
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Debug in depth
C.5
C.5.1
C.5.2
C-10
Test data registers
Bypass register
ARM9E-S device identification (ID) code register
There are six test data registers that can be selected to connect between DBGTDI and
DBGTDO:
•
•
•
•
•
•
In addition, other scan chains can be added between DBGSDOUT and DBGSDIN, and
selected when in INTEST mode.
In the following descriptions, data is shifted during every CLK cycle when
DBGTCKEN enable is HIGH.
Purpose
Length
Operating mode
Purpose
Length
bypass register
scan path select register
scan chain 1
scan chain 2.
ID code register
instruction register
Copyright © 2000 ARM Limited. All rights reserved.
Bypasses the device during scan testing by providing a path
between DBGTDI and DBGTDO.
1 bit.
When the BYPASS instruction, or any undefined instruction, is
the current instruction in the instruction register, serial data is
transferred from DBGTDI to DBGTDO in the SHIFT-DR state
with a delay of one CLK cycle enabled by DBGTCKEN.
A logic 0 is loaded from the parallel input of the bypass register in
the CAPTURE-DR state. There is no parallel output from the
bypass register.
Reads the 32-bit device identification code. No programmable
supplementary identification code is provided.
32 bits. The format of the ID register is shown in Figure C-3 on
page C-11.
The 32-bit device identification code is loaded into the register
from the parallel inputs of the TAPID[31:0] input pins during the
CAPTURE-DR state.
ARM DDI 0165B
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