SAM9G10 Atmel Corporation, SAM9G10 Datasheet

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... Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals ® ® Thumb Processor ® Acceleration ® Product Description AT91SAM9G10 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6462AS–ATARM–03-Jun-09 ...

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... Required Power Supplies: – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and for VDDPLL – 2.7V to 3.6V for VDDIOP (Peripheral I/Os) – 1.65V to 3.6V for VDDIOM (Memory I/Os) • Available in a 217-ball LFBGA RoHS-compliant Package AT91SAM9G10 2 ™ Compliant ® Infrared Modulation/Demodulation 6462AS–ATARM–03-Jun-09 ...

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... The AT91SAM9G10 also benefits from the integration of a wide range of debug features includ- ing JTAG-ICE, a dedicated UART debug channel (DBGU). This enables the development and debug of all applications, especially those with real-time constraints. ...

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... Block Diagram Figure 2-1. AT91SAM9G10 Block Diagram JTAGSEL TDI JTAG TDO TMS Boundary Scan TCK NTRST RTCK System Controller TST AIC FIQ IRQ0-IRQ2 DRXD DBGU DTXD PDC PCK0-PCK3 PLLRCA PLLA PLLRCB PMC PLLB XIN OSC XOUT WDT PIT GPBREG XIN32 OSC RTT ...

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... Input Output Input Input Low Input Reset/Test I/O Low Input Input Debug Unit Input Output AT91SAM9G10 Comments 1. 1.95V and 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V Do not tie over VDDBU. Accepts between 0V and VDDBU. No pull-up resistor. No pull-up resistor. No pull-up resistor. No pull-up resistor. ...

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... BA0 - BA1 Bank Select SDWE SDRAM Write Enable RAS - CAS Row and Column Signal SDA10 SDRAM Address 10 Line MCCK Multimedia Card Clock MCCDA Multimedia Card A Command MCDA0 - MCDA3 Multimedia Card A Data AT91SAM9G10 6 Type Active Level AIC Input Input PIO I/O I/O I/O EBI I/O Output ...

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... USB Device Port Data + 6462AS–ATARM–03-Jun-09 Type Active Level USART I/O Output Input Output Input Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter Input I/O I/O SPI I/O I/O I/O I/O Low Output Low Two-Wire Interface I/O I/O LCD Controller Output Output Output Output Output Output USB Device Port Analog Analog AT91SAM9G10 Comments 7 ...

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... Signal Description by Peripheral (Continued) Signal Name Function HDMA USB Host Port A Data - HDPA USB Host Port A Data + HDMB USB Host Port B Data - HDPB USB Host Port B Data + AT91SAM9G10 8 Type Active Level USB Host Port Analog Analog Analog Analog Comments 6462AS–ATARM–03-Jun-09 ...

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... Package and Pinout The AT91SAM9G10 is available in a 217-ball LFBGA RoHS-compliant package mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9G10 Mechanical Charac- teristics” of the product datasheet. Figure 4-1. 6462AS–ATARM–03-Jun-09 shows the orientation of the 217-ball LFBGA Package. ...

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... Pinout Table 4-1. AT91SAM9G10 Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 A19 D5 A2 A16/BA0 D6 A3 A14 D7 A4 A12 D10 A7 A3 D11 A8 A2 D12 A9 NC D13 A10 XOUT32 D14 A11 XIN32 D15 A12 DDP D16 A13 HDPB D17 ...

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... Power Considerations 5.1 Power Supplies The AT91SAM9G10 has six types of power supply pins: • VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to 1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal. • ...

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... This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU. AT91SAM9G10 12 6462AS–ATARM–03-Jun-09 ...

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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 6462AS–ATARM–03-Jun-09 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9G10 13 ...

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... Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the Multimedia Card Interface AT91SAM9G10 14 Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. ...

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... Memories Figure 8-1. AT91SAM9G10 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3/ ...

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... Slave 4 8.1 Embedded Memories • ROM – Single Cycle Access at full bus speed • Fast SRAM – Single Cycle Access at full bus speed AT91SAM9G10 16 ™ Instruction and Data), three different Slaves are Table 8-3 for details. List of Bus Matrix Masters List of Bus Matrix Slaves ...

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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9G10 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. ...

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... Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock 4. Switch the main clock to the new value. 8.2 External Memories The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3). Refer to the memory map in AT91SAM9G10 18 Figure 8-1 on page 15. 6462AS–ATARM–03-Jun-09 ...

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... EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 20 Figure 8-1 on page 15 peripherals. 6462AS–ATARM–03-Jun-09 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller AT91SAM9G10 19 ...

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... SLOW CLOCK XOUT32 OSC XIN MAIN OSC XOUT PLLRCA PLLA PLLRCB PLLB periph_nreset usb_suspend periph_nreset periph_clk[2..4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 AT91SAM9G10 20 System Controller irq0-irq2 Advanced fiq Interrupt Controller int MCK dbgu_irq Debug force_ntrst Unit dbgu_txd MCK Periodic debug Interval pit_irq Timer ...

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... Clock Generator Block Diagram Clock Generator XIN32 Slow Clock Oscillator XOUT32 XIN Main Oscillator XOUT PLL and PLLRCA Divider A PLL and PLLRCB Divider B Status Power Management Controller AT91SAM9G10 Slow Clock SLCK Main Clock MAINCK PLLA Clock PLLACK PLLB Clock PLLBCK Control 21 ...

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... Windowed, prevents the processor dead-lock on the watchdog access 9.9 Real-time Timer • 32-bit Free-running backup counter • Alarm Register capable to generate a wake-up of the system AT91SAM9G10 22 Power Management Controller Block Diagram Master Clock Controller SLCK Divider ...

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... Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support 6462AS–ATARM–03-Jun-09 interrupts processor Generator AT91SAM9G10 23 ...

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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write AT91SAM9G10 24 peripherals 6462AS–ATARM–03-Jun-09 ...

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... Note: 6462AS–ATARM–03-Jun-09 Figure 8-1 on page defines the Peripheral Identifiers of the AT91SAM9G10. A peripheral identifier is Peripheral Identifiers Peripheral Mnemonic AIC SYSIRQ PIOA PIOB PIOC - US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC0 ...

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... Peripheral Multiplexing on PIO Lines The AT91SAM9G10 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions page 30 lers. The two columns “Function” and “Comments” have been inserted for the user’s own comments ...

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... Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and/or USART0. 10.3.1.9 Interrupt Lines • Using FIQ prevents using the USART0 control signals. • Using IRQ0 prevents using the NWAIT EBI signal. • Using the IRQ1 and/or IRQ2 prevents using the SPI1. 6462AS–ATARM–03-Jun-09 AT91SAM9G10 27 ...

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... PA24 TPK8 SPI1_NPCS1 PA25 TPK9 SPI1_NPCS2 PA26 TPK10 SPI1_NPCS3 PA27 TPK11 SPI0_NPCS1 PA28 TPK12 SPI0_NPCS2 PA29 TPK13 SPI0_NPCS3 PA30 TPK14 A23 PA31 TPK15 A24 AT91SAM9G10 28 Application Usage Reset Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP ...

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... Comments State Power Supply I/O I/O I/O (1) See footnote I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AT91SAM9G10 Function Comments VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP 29 ...

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... PC24 D24 TIOB2 PC25 D25 TF2 PC26 D26 TK2 PC27 D27 TD2 PC28 D28 RD2 PC29 D29 RK2 PC30 D30 RF2 PC31 D31 PCK1 AT91SAM9G10 30 Application Usage Reset Comments State Power Supply I/O VDDIOM I/O VDDIOP I/O VDDIOP A25 VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOM I/O ...

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... Static Memory Controller on NCS3, Optional NAND Flash Support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support – Static Memory Controller on NCS6 - NCS7 6462AS–ATARM–03-Jun-09 IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. AT91SAM9G10 31 ...

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... Energy-saving Capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not used AT91SAM9G10 32 6462AS–ATARM–03-Jun-09 ...

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... Optional break generation and detection – By-8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding 6462AS–ATARM–03-Jun-09 fifteen peripherals Sensors and data per chip select AT91SAM9G10 33 ...

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... Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.1 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used AT91SAM9G10 TDM Buses, Magnetic Card Reader and ...

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... TFT • Single clock domain architecture • Resolution supported up to 1280 x 860 6462AS–ATARM–03-Jun-09 Endpoint 0: 8 bytes, no ping-pong mode Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode Endpoint 3: 64 bytes, no ping-pong mode Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode AT91SAM9G10 35 ...

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... Package Drawing Figure 11-1. 217-ball LFBGA Package Drawing AT91SAM9G10 36 6462AS–ATARM–03-Jun-09 ...

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... AT91SAM9G10 Ordering Information Table 12-1. AT91SAM9G10 Ordering Information Ordering Code AT91SAM9G10-CU 6462AS–ATARM–03-Jun-09 Package Package Type BGA217 RoHS-compliant AT91SAM9G10 Temperature Operating Range Industrial -40°C to 85°C 37 ...

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... Revision History Doc. Rev Comments 6462AS First issue AT91SAM9G10 38 Change Request Ref. 6462AS–ATARM–03-Jun-09 ...

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