SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1065

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
45.6
45.6.1
45.6.1.1
45.6.1.2
45.6.1.3
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Functional Description
Timing Engine Configuration
Pixel Clock Period Configuration
Horizontal and Vertical Synchronization Configuration
Timing Engine Power Up Software Operation
The LCD module integrates the following digital blocks:
The DMA controller reads the image through the AHB master interface. The LCD controller
engine formats the display data, then the GAB performs alpha blending if required, and writes
the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the
LCD_DAT[23:0] display bus.
The pixel clock (PCLK) generated by the timing engine is the source clock (SCLK) divided by the
field CLKDIV in the LCDC_LCDCFG0 register. The source clock can be selected between the
system clock and the 2x system clock with the field CLKSEL located in the LCDC_LCDCFG0
register. The Pixel Clock period formula is given below:
The Pixel Clock polarity is also programmable.
The following fields are used to configure the timing engine:
The polarity of output signals is also programmable.
The following sequence is used to enable the display:
• DMA Engine Address Generation (DEAG). This block performs data prefetch and requests
• Input FIFO, stores the stream of pixels.
• Color Lookup Table (CLUT). These 256 RAM-based lookup table entries are selected when
• Chroma Upsampling Engine (CUE). This block is selected when the input image sampling
• Color Space Conversion (CSC), changes the color space from YUV to RGB.
• Two Dimension Scaler (2DSC), resizes the image.
• Global Alpha Blender (GAB), performs programmable 256 level alpha blending.
• Output FIFO, stores the pixel prior to display.
• LCD Timing Engine, provides a fully programmable HSYNC-VSYNC interface.
• HSPW field
• VSPW field
• VFPW field
• VBPW field
• HFPW field
• HBPW field
• PPL field
• RPF field
access to the AHB interface.
the color depth is set to 1, 2, 4 or 8 bpp.
format is YUV (Y’CbCr) 4:2:0 and converts it to higher quality 4:4:4 image.
PCLK
=
--------------------------------
CLKDIV
SCLK
+
2
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