SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1066

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
45.6.1.4
1066
1066
SAM9G35
SAM9G35
Timing Engine Power Down Software Operation
The GUARDTIME field of the LCDC_LCDCFG5 register is used to configure the number of
frames before the assertion of the DISP signal.
The following sequence is used to disable the display:
1. Configure LCD timing parameters, signal polarity and clock period.
2. Enable the Pixel Clock by writing one to the CLKEN field of the LCDC_LCDEN register.
3. Poll CLKSTS field of the LCDC_LCDSR register to check that the clock is running.
4. Enable Horizontal and Vertical Synchronization by writing one to the SYNCEN field of
5. Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is
6. Enable the display power signal writing one to the DISPEN field of the LCDC_LCDEN
7. Poll DISPSTS field of the LCDC_LCDSR register to check that the power signal is
1. Disable the DISP signal writing DISPDIS field of the LCDC_LCDDIS register.
2. Poll DISPSTS field of the LCDC_LCDSR register to verify that the DISP is no longer
3. Disable the hsync and vsync signals by writing one to SYNCDIS field of the
4. Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is
5. Disable the Pixel clock by writing one in the CLKDIS field of the LCDC_LCDDIS
the LCDC_LCDEN register.
up.
register.
activated.
activated.
LCDC_LCDDIS register.
off.
register.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11

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