SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1082

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.6.6.1
45.6.7
45.6.7.1
45.6.7.2
45.6.8
1082
1082
SAM9G35
SAM9G35
Line and Pixel Striding
Color Space Conversion Unit
Chrominance Upsampling Algorithm
Line Striding
Pixel Striding
The LCD module includes a mechanism to increment the memory address from a programma-
ble amount when the end of line has been reached, this offset is referred as XSTRIDE and is
defined on a per overlay basis. It also contains a PSTRIDE field that allows a programmable
jump at the pixel level. Pixel stride is the value from one pixel to the next.
When the end of line has been reached, the DMA address counter points to the next pixel
address. The channel DMA address register is added to the XSTRIDE field, and then updated. If
XSTRIDE is set to zero, the DMA address register remains unchanged. The XSTRIDE field of
the channel configuration register is aligned to the pixel size boundary. The XSTRIDE field is a
two’s complement number.
The DMA channel engine may optionally fetch non contiguous pixels. The channel DMA
address register is added to the PSTRIDE field and then updated. If PSTRIDE is set to zero, the
DMA address register remains unchanged and pixels are contiguous. The PSTRIDE field of the
channel configuration register is aligned to the pixel size boundary. The PSTRIDE is a two’s
complement number.
The color space conversion unit converts Luminance Chrominance color space into the Red
Green Blue color space. The conversion matrix is defined below and is fully programmable
through the LCD user interface
Color space conversion coefficients are defined with the following equation:
1. Read line n from chrominance cache and interpolate [x/2,0] chrominance component
2. Fetch line n+1 from external memory, write line n + 1 to chrominance cache, read line n
3. Repeat step 1 and step 2.
filling the 1 x 2 kernel with line n. If the chrominance cache is empty, then fetch the first
line from external memory and interpolate from the external memory. Duplicate the last
chrominance at the end of line.
from the chrominance cache. interpolate [0,y/2], [x/2,y/2] and [x, y/2] filling the 2x2 ker-
nel with line n and n+1. Duplicate the last chrominance line to generate the last
interpolated line.
G
R
B
CSC
=
Note
CSCGY CSCGU CSCGV
CSCRY CSCRU CSCRV
CSCBY CSCBU CSCBV
=
----- -
2
1
7
–
2
9
c
9
+
n
8
=
0
c
Cb Cboff
Cr Croff
n
Y Yoff
2
–
–
–
n
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11