SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1095

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.7
Table 45-55. Register Mapping
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
0x0000000C
0x0000001C
0x0000002C
0x0000003C
0x0000004C
0x0000005C
0x0000006C
0x0000007C
0x0000010C
0x00000000
0x00000004
0x00000008
0x00000010
0x00000014
0x00000018
0x00000020
0x00000024
0x00000028
0x00000030
0x00000034
0x00000038
0x00000040
0x00000044
0x00000048
0x00000050
0x00000054
0x00000058
0x00000060
0x00000064
0x00000068
0x00000070
0x00000074
0x00000078
0x00000100
0x00000104
0x00000108
0x80-0xFC
Offset
LCD Controller (LCDC) User Interface
Register
LCD Controller Configuration Register 0
LCD Controller Configuration Register 1
LCD Controller Configuration Register 2
LCD Controller Configuration Register 3
LCD Controller Configuration Register 4
LCD Controller Configuration Register 5
LCD Controller Configuration Register 6
Reserved
LCD Controller Enable Register
LCD Controller Disable Register
LCD Controller Status Register
LCD Controller Interrupt Enable Register
LCD Controller Interrupt Disable Register
LCD Controller Interrupt Mask Register
LCD Controller Interrupt Status Register
Reserved
Base Layer Channel Enable Register
Base Layer Channel Disable Register
Base Layer Channel Status Register
Base Layer Interrupt Enable Register
Base Layer Interrupt Disabled Register
Base Layer Interrupt Mask Register
Base Layer Interrupt status Register
Base Layer DMA Head Register
Base Layer DMA Address Register
Base Layer DMA Control Register
Base Layer DMA Next Register
Base Layer Configuration Register 0
Base Layer Configuration Register 1
Base Layer Configuration Register 2
Base Layer Configuration Register 3
Base Layer Configuration Register 4
Reserved
Overlay 1 Channel Enable Register
Overlay 1 Channel Disable Register
Overlay 1 Channel Status Register
Overlay 1 Interrupt Enable Register
LCDC_OVRCHDR1
LCDC_BASECHER
LCDC_BASECHDR
LCDC_BASECHSR
LCDC_BASEHEAD
LCDC_BASEADDR
LCDC_OVRCHER1
LCDC_OVRCHSR1
LCDC_BASENEXT
LCDC_BASECFG0
LCDC_BASECFG1
LCDC_BASECFG2
LCDC_BASECFG3
LCDC_BASECFG4
LCDC_BASECTRL
LCDC_LCDCFG0
LCDC_LCDCFG1
LCDC_LCDCFG2
LCDC_LCDCFG3
LCDC_LCDCFG4
LCDC_LCDCFG5
LCDC_LCDCFG6
LCDC_BASEIMR
LCDC_BASEIDR
LCDC_BASEIER
LCDC_BASEISR
LCDC_OVRIER1
LCDC_LCDIDR
LCDC_LCDIMR
LCDC_LCDDIS
LCDC_LCDIER
LCDC_LCDISR
LCDC_LCDEN
LCDC_LCDSR
Name
–
–
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Write-only
Access
–
–
–
SAM9G35
SAM9G35
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
–
–
–
–
–
-
-
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