SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1104

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.7.6
Name:
Address:
Access:
Reset:
• HSPOL: Horizontal Synchronization Pulse Polarity
0: Active High
1: Active Low
• VSPOL: Vertical Synchronization Pulse Polarity
0: Active High
1: Active Low
• VSPDLYS: Vertical Synchronization Pulse Start
0: The first active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse.
1: The first active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse.
• VSPDLYE: Vertical Synchronization Pulse End
0: The second active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal
pulse.
1: The second active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse.
• DISPPOL: Display Signal Polarity
0: Active High
1: Active Low
• DITHER: LCD Controller Dithering
0: Dithering logical unit is disabled.
1: Dithering logical unit is activated.
• DISPDLY: LCD Controller Display Power Signal Synchronization
0: the LCD_DISP signal is asserted synchronously with the second active edge of the horizontal pulse.
1: the LCD_DISP signal is asserted asynchronously with both edges of the horizontal pulse.
1104
1104
DISPDLY
31
23
15
–
–
–
7
SAM9G35
SAM9G35
LCD Controller Configuration Register 5
LCDC_LCDCFG5
0xF8038014
Read-write
0x00000000
DITHER
30
22
14
–
–
–
6
VSPHO
29
21
13
–
–
5
–
DISPPOL
VSPSU
28
20
12
–
4
VSPDLYE
27
19
11
–
–
3
GUARDTIME
VSPDLYS
26
18
10
–
–
2
VSPOL
25
17
–
9
1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
MODE
HSPOL
24
16
–
8
0