SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1237

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.15 SMC Timings
46.15.1
46.15.2
46.15.2.1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Timing Conditions
Timing Extraction
Zero Hold Mode Restrictions
The T
(44KHz).
As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to
ensure a reliable operation of the device.
SMC Timings are given for MAX corners.
Timings are given assuming a capacitance load on data, control and address pads:
Table 46-29. Capacitance Load
In the following tables, t
Table 46-30. Zero Hold Mode Use Maximum system clock frequency (MCK)
Supply
3.3V
1.8V
Symbol
Fmax
• VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled
into the ROM code.
– T
– T1 = 66 μs
– T2 = 352 μs
SLCK
RES
min (22 μs) is obtained for the maximum frequency of the internal RC oscillator
= 30 μs
Parameter
VDDIOM supply
MCK frequency
MAX
50pF
30 pF
CPMCK
Corner
is MCK period.
5 pF
5 pF
MIN
Zero Hold Mode Use
1.8V
66
Min
3.3V
66
SAM9G35
SAM9G35
Units
MHz
1237
1237