SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 273

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

24.4
24.4.1
24.4.2
24.4.3
24.5
24.5.1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Product Dependencies
UART Operations
I/O Lines
Power Management
Interrupt Source
Baud Rate Generator
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this
case, the programmer must first configure the corresponding PIO Controller to enable I/O lines
operations of the Debug Unit.
Table 24-2.
Depending on product integration, the Debug Unit clock may be controllable through the Power
Management Controller. In this case, the programmer must first configure the PMC to enable the
Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.
Depending on product integration, the Debug Unit interrupt line is connected to one of the inter-
rupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of
the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the
interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer
interrupt lines and other system peripheral interrupts, as shown in
requires the programmer to determine the source of the interrupt when the source 1 is triggered.
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit charac-
ter handling (with parity). It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently,
and a common baud rate generator. Receiver timeout and transmitter time guard are not imple-
mented. However, all the implemented features are compatible with those of a standard USART.
The baud rate generator provides the bit period clock named baud rate clock to both the receiver
and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in
DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock
is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is
Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x
65536).
Instance
DBGU
DBGU
I/O Lines
Signal
DRXD
DTXD
Baud Rate
=
-------------------- -
16
MCK
CD
I/O Line
PA10
PA9
Figure
Peripheral
24-1. This sharing
SAM9G35
SAM9G35
A
A
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