SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 297

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
25.4
Table 25-1.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Name
EBI_D0 - EBI_D31
EBI_A0 - EBI_A25
EBI_NWAIT
EBI_NCS0 - EBI_NCS5
EBI_NWR0 - EBI_NWR3
EBI_NRD
EBI_NWE
EBI_NBS0 - EBI_NBS3
EBI_NANDCS
EBI_NANDOE
EBI_NANDWE
EBI_SDCK, EBI_SDCK#
EBI_SDCKE
EBI_SDCS
EBI_BA0 - 2
EBI_SDWE
EBI_RAS - EBI_CAS
EBI_SDA10
I/O Lines Description
EBI I/O Lines Description
The connection of some signals through the MUX logic is not direct and depends on the Memory
Controller in use at the moment.
Table 25-2 on page 297
EBI pins.
Table 25-2.
EBI_NWR1/NBS1/CFIOR
EBI_A0/NBS0
EBI_A1/NBS2/NWR2
EBI_A[11:2]
EBI_SDA10
EBI_A12
EBI_A[14:13]
EBI_A[25:15]
EBI_D[31:0]
Chip Select Lines
Read Signal
NAND Flash Chip Select Line
NAND Flash Output Enable
NAND Flash Write Enable
DDR2/SDRAM Differential Clock
DDR2/SDRAM Clock Enable
SDRAM Address 10 Line
Function
Data Bus
Address Bus
External Wait Signal
Write Signals
Write Enable
Byte Mask Signals
DDR2/SDRAM Controller Chip Select Line
Bank Select
DDR2/SDRAM Write Enable
Row and Column Signal
EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins
EBI for NAND Flash Support
DDR2/SDRAM Controller
details the connections between the two Memory Controllers and the
SMC
EBI
NBS1
Not Supported
Not Supported
SDRAMC_A[9:0]
SDRAMC_A10
Not Supported
SDRAMC_A[12:11]
Not Supported
D[31:0]
SDRAM I/O Lines
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
NWR1
SMC_A0
SMC_A1
SMC_A[11:2]
Not Supported
SMC_A12
SMC_A[14:13]
SMC_A[25:15]
D[31:0]
SAM9G35
SAM9G35
SMC I/O Lines
Active Level
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
297
297

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