SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 300

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.5.2
25.5.2.1
25.5.3
25.5.3.1
25.5.3.2
300
300
SAM9G35
SAM9G35
Product Dependencies
Functional Description
I/O Lines
Bus Multiplexing
Pull-up and Pull-down Control
Table 25-4.
Note:
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control buses and is composed of the following elements:
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 26 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the DDR2 and SDRAM are executed independently by the DDR2SDR Control-
ler without delaying the other external Memory Controller accesses.
The EBI_CSA registers in the Chip Configuration User Interface enable on-chip pull-up and pull-
down resistors on data bus lines not multiplexed with the PIO Controller lines. The pull-down
resistors are enabled after reset. The bits, EBIx_DBPUC and EBI_DBPDC, control the pull-up
Signals:
EBI_
Controller
RAS
CAS
SDWE
Pxx
Pxx
• the Static Memory Controller (SMC)
• the DDR2/SDRAM Controller (DDR2SDRC)
• the Programmable Multi-bit ECC Controller (PMECC)
• a chip select assignment feature that assigns an AHB address space to the external devices
• a multiplex controller circuit that shares the pins between the different Memory Controllers
• programmable NAND Flash support logic
1. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 or D16-D24
depending on memory power supplies. This switch is located in the EBICSA register in the Bus
Matrix user interface.
EBI Pins and External Device Connections
Power supply
VDDIOM
VDDIOM
VDDIOM
VDDNF
VDDNF
DDR2/LPDDR
DDRC
RAS
CAS
WE
–
–
Pins of the Interfaced Device
SDR/LPSDR
SDRAMC
RAS
CAS
WE
–
–
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
NAND Flash
NFC
RDY
CE
–
–
–