SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 307

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.5.4.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Hardware Configuration
Software Configuration
16-bit LPDDR on EBI
The following configuration has to be performed:
The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Ini-
tialization” in “DDR/SDR SDRAM Controller (DDRSDRC)”.
In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V
and wired on D16-D31 data bus. NFD0_ON_D16 is to be set to 1.
• Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select
• Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency.
Register located in the bus matrix memory space.
SAM9G35
SAM9G35
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