SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 318

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

26.3
26.4
26.4.1
26.4.2
318
Memory Mapping
Special Bus Granting Mechanism
SAM9G35
No Default Master
Last Access Master
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each
AHB master several memory mappings. Each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM
or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR),
that performs remap action for every master independently.
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from masters. This mechanism reduces latency at first access of a burst, or single
transfer, as long as the slave is free from any other master access, but does not provide any
benefit as soon as the slave is continuously accessed by more than one master, since arbitra-
tion is pipelined and has no negative effect on the slave bandwidth or access latency.
This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters:
To change from one type of default master to another, the Bus Matrix user interface provides the
Slave Configuration Registers, one for every slave, that set a default master for each slave. The
Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The
2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed
default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master pro-
vided that DEFMSTR_TYPE is set to fixed default master. Refer to
Slave Configuration
After the end of the current access, if no other request is pending, the slave is disconnected from
all masters.
This configuration incurs one latency clock cycle for the first access of a burst after bus Idle.
Arbitration without default master may be used for masters that perform significant bursts or sev-
eral transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or
more masters.
This configuration provides no benefit on access latency or bandwidth when reaching maximum
slave bus throughput, irregardless of the number of requesting masters.
After the end of the current access, if no other request is pending, the slave remains connected
to the last master that performed an access request.
This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the
slave. Other non-privileged masters still get one latency clock cycle if they want to access the
same slave. This technique is useful for masters that mainly perform single accesses or short
bursts with some Idle cycles in between.
• no default master
• last access master
• fixed default master
Registers”.
Section 26.7.2 “Bus Matrix
11053B–ATARM–22-Sep-11