SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 32

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
32
32
ARM9EJ-S Processor
SAM9G35
SAM9G35
ARM9EJ-S Operating States
Switching State
Instruction Pipelines
Memory Access
Jazelle Technology
The ARM9EJ-S processor can operate in three different states, each with a specific instruction
set:
In Jazelle state, all instruction Fetches are in words.
The operating state of the ARM9EJ-S core can be switched between:
All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or
Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle
states occurs automatically on return from the exception handler.
The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions
to the processor.
A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch,
Decode, Execute, Memory and Writeback stages.
A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch,
Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages.
The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words
must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and
bytes can be placed on any byte boundary.
Because of the nature of the pipelines, it is possible for a value to be required for use before it
has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S con-
trol logic automatically detects these cases and stalls the core or forward data.
The Jazelle technology enables direct and efficient execution of Java byte codes on ARM pro-
cessors, providing high performance for the next generation of Java-powered wireless and
embedded devices.
The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java
Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb
instructions, it executes Java byte codes. The Java byte code decoder logic implemented in
ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without
any overhead, while less frequently used byte codes are broken down into optimized sequences
of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the
application and invisible to the operating system. All existing ARM registers are re-used in
Jazelle state and all registers then have particular functions in this mode.
• ARM state: 32-bit, word-aligned ARM instructions.
• THUMB state: 16-bit, halfword-aligned Thumb instructions.
• Jazelle state: variable length, byte-aligned Jazelle instructions.
• ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
• ARM state and Jazelle state using the BXJ instruction
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11