SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 325

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

26.7.1
Name:
Address:
Access:
• ULBT: Undefined Length Burst Type
0: Unlimited Length Burst
No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot
Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on
the next AHB 1 KByte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR
burst.
2: 4-beat Burst
The undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end.
3: 8-beat Burst
The undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end.
4: 16-beat Burst
The undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end.
5: 32-beat Burst
The undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end.
6: 64-beat Burst
The undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end.
7: 128-beat Burst
The undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end.
Unless duly needed, the ULBT should be left at its default 0 value for power saving.
11053B–ATARM–22-Sep-11
31
23
15
–
–
–
7
–
Bus Matrix Master Configuration Registers
MATRIX_MCFG0...MATRIX_MCFG10
0xFFFFDE00 [0], 0xFFFFDE04 [1], 0xFFFFDE08 [2], 0xFFFFDDEC [3], 0xFFFFDE10 [4], 0xFFFFDE14 [5],
0xFFFFDE18 [6], 0xFFFFDE1C [7], 0xFFFFDE20 [8], 0xFFFFDE24 [9], 0xFFFFDE28 [10]
Read-write
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
ULBT
25
17
–
–
9
–
1
SAM9G35
24
16
–
–
8
–
0
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