SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 339

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

27.4.1
27.4.1.1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
MLC/SLC Write Page Operation using PMECC
SLC/MLC Write Operation with Spare Enable Bit Set
When an MLC write page operation is performed, the PMECC controller is configured with the
NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file
system information and redundancy (PMECCx), the spare area is error protected, then the SPA-
REEN bit of the PMECCFG register is set to one. When the NAND spare area contains only
redundancy information, the SPAREEN bit is set to zero.
When the write page operation is terminated, the user writes the redundancy in the NAND spare
area. This operation can be done with DMA assistance.
Table 27-1.
Table 27-2.
When the SPAREEN field of the PMECC_CFG register is set to one, the spare area of the page
is encoded with the stream of data of the last sector of the page. This mode is entered by writing
one in the DATA field of the PMECC_CTRL register. When the encoding process is over, the
redundancy is written to the spare area in user mode, USER field of the PMECC_CTRL must be
set to one.
BCH_ERR field
0
1
2
3
4
BCH_ERR field
0
1
2
3
4
Relevant Redundancy Registers
Number of relevant ECC bytes per sector, copied from LSbyte to MSbyte
sector size set to 512 bytes
PMECC_ECC0
PMECC_ECC0, PMECC_ECC1
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6, PMECC_ECC7,
PMECC_ECC8, PMECC_ECC9
sector size set to 512 bytes
4 bytes
7 bytes
13 bytes
20 bytes
39 bytes
sector size set to 1024 bytes
PMECC_ECC0
PMECC_ECC0, PMECC_ECC1
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6, PMECC_ECC7,
PMECC_ECC8, PMECC_ECC9,
PMECC_ECC10
sector size set to 1024 bytes
4 bytes
7 bytes
14 bytes
21 bytes
42 bytes
SAM9G35
SAM9G35
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