SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 394

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

29.9.5
29.9.6
394
394
SAM9G35
SAM9G35
Write Protected Registers
Coding Timing Parameters
Figure 29-15. WRITE_MODE = 0. The write operation is controlled by NCS
To prevent any single software error that may corrupt SMC behavior, the registers listed below
can be write-protected by setting the WPEN bit in the SMC Write Protect Mode Register
(SMC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write
Protect Status Register (SMC_WPSR) is set and the field WPVSRC indicates in which register
the write access has been attempted.
The WPVS flag is automatically reset after reading the SMC Write Protect Status Register
(SMC_WPSR).
List of the write-protected registers:
All timing parameters are defined for one chip select and are grouped together in one
SMC_REGISTER according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
•
•
•
•
•
Section 29.16.1 ”SMC Setup Register”
Section 29.16.2 ”SMC Pulse Register”
Section 29.16.3 ”SMC Cycle Register”
Section 29.16.4 ”SMC MODE Register”
Section 29.16.5 ”SMC DELAY I/O Register”
NWR0, NWR1,
NWR2, NWR3
NBS0, NBS1,
NBS2, NBS3,
A0, A1
D[31:0]
A
NWE,
[25:2]
MCK
NCS
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11