SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 442

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Figure 30-15. Burst Read Access, Latency = 3, DDR2-SDRAM Devices
Figure 30-16. Burst Read Access, Latency = 2, SDR-SDRAM Devices
30.5.3
442
442
COMMAND
COMMAND
DQS[1:0]
DQS[1:0]
DM[3:0]
SDCLK
BA[1:0]
DM[1:0]
D[31:0]
A[12:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
SAM9G35
SAM9G35
Refresh (Auto-refresh Command)
NOP
0
NOP
0
3
col a
READ
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated
internally by the SDRAM device and incremented after each auto-refresh automatically. The
DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the
value in the register DDRSDRC_TR that indicates the number of clock cycles between refresh
cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM device, the slave indicates that
the device is busy. A request of refresh does not interrupt a burst transfer in progress.
Col a
READ
F
Latency = 2
NOP
Latency = 3
NOP
DaDb
DcDd
Da
DeDf
Db
BST
Dc
Dd
Dg Dh
De
NOP
Df
Dg
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Dh

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