SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 464

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.7.6
Name:
Address:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
The Reset Value is 2 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.
The Reset Value is 6 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRPA: Row Precharge All Delay
The Reset Value is 0 cycle.
This field defines the delay between a Precharge ALL banks Command and another command in number of cycles. Num-
ber of cycles is between 0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRTP: Read to Precharge
The Reset Value is 2 cycles.
This field defines the delay between Read Command and a Precharge command in number of cycle.
Number of cycles is between 0 and 7.
• TFAW: Four Active window
The Reset Value is 4 cycles.
DDR2 devices with 8-banks (1Gb or larger) have an additional requirement: t
ACTIVATE commands may be issued in any given t
Number of cycles is between 0 and 15.
Note: This field is found only in DDR-SDRAM 2 devices with eight internal banks
464
464
31
23
15
–
–
7
SAM9G35
SAM9G35
DDRSDRC Timing Parameter 2 Register
30
22
14
DDRSDRC_TPR2
0xFFFFE814
Read-write
See
–
–
6
TXARDS
Table 30-16
TRTP
29
21
13
5
–
–
FAW
28
20
12
4
–
–
(MIN) period.
“DDRSDRC Write Protect Mode Register” on page
27
19
11
3
–
FAW
. This requires that no more than four
26
18
10
2
–
TXARD
TRPA
TFAW
25
17
9
1
–
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
470.
24
16
8
0
–