SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 486

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

486
486
Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)
SAM9G35
SAM9G35
4. After the DMAC selected channel has been programmed, enable the channel by writing
5. Source and destination request single and chunk DMAC transactions to transfer the
6. Once the transfer completes, hardware sets the interrupts and disables the channel. At
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in mem-
3. Write the channel configuration information into the DMAC_CFGx register for
4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory
– ii. If the hardware handshaking interface is activated for the source or destination
g. If source picture-in-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is
h. If destination picture-in-picture mode is enabled (DMAC_CTRLBx.DST_PIP is
a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n is the channel number. Make sure
that bit 0 of DMAC_EN.ENABLE register is enabled.
buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
this time you can either respond to the buffer Complete or Transfer Complete interrupts,
or poll for the Channel Handler Status Register (DMAC_CHSR.ENABLE[n]) bit until it is
cleared by hardware, to detect when the transfer is complete.
ory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx
registers location of the buffer descriptor for each LLI in memory (see
page
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
channel x.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
(except the last) are set as shown in Row 4 of
LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in
peripheral, assign a handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
enabled), program the DMAC_SPIPx register for channel x.
enabled), program the DMAC_DPIPx register for channel x.
nation) and flow control device by programming the FC of the DMAC_CTRLBx
register.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface to han-
dle source/destination requests.
peripheral, assign the handshaking interface to the source and destination periph-
eral. This requires programming the SRC_PER and DST_PER bits, respectively.
488) for channel x. For example, in the register, you can program the following:
Table 31-3 on page
483. The
Figure 31-6 on
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11