SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 492

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

492
492
SAM9G35
SAM9G35
Figure 31-9. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded
6. The DMAC transfer proceeds as follows:
Channel Enable in the Channel Status Register (DMAC_CHSR.ENABLE[n]) until it is
disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
number) hardware sets the buffer complete interrupt when the buffer transfer has
completed. It then stalls until the STALLED[n] bit of DMAC_CHSR register is
cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit in the DMAC_CTRLBx.AUTO bit. This put the DMAC into Row 1 as shown in
Table 31-3 on page
fer, then the reload bits should remain enabled to keep the DMAC in Row 4.
the channel number), then hardware does not stall until it detects a write to the buf-
fer complete interrupt enable register DMAC_EBCIER register but starts the next
buffer transfer immediately. In this case software must clear the automatic mode bit
in the DMAC_CTRLB to put the DMAC into ROW 1 of
before the last buffer of the DMAC transfer has completed. The transfer is similar to
that shown in
31-10 on page
Source Layer
Address of
SADDR
Figure 31-9 on page
493.
Source Buffers
483. If the next buffer is not the last buffer in the DMAC trans-
492. The DMAC transfer flow is shown in
Block2
Block0
Block1
BlockN
Destination Buffers
Table 31-3 on page 483
DADDR
Destination Layer
Address of
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Figure