SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 494

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

494
494
SAM9G35
SAM9G35
Note:
Note:
3. Write the starting source address in the DMAC_SADDRx register for channel x.
4. Write the channel configuration information into the DMAC_CFGx register for
5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
7. Make sure that the LLI.DMAC_DADDRx register location of all LLIs in memory point to
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register
9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
11. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 6 as shown in
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
16. Source and destination request single and chunk DMAC transactions to transfer the
17. The DMAC_CTRLAx register is written out to system memory. The DMAC_CTRLAx
channel x.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
the last) are set as shown in Row 6 of
LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in
Row 1 of
list items.
the last) are non-zero and point to the next Linked List Item.
the start destination buffer address proceeding that LLI fetch.
locations of all LLIs in memory is cleared.
DMAC_SPIPx register for channel x.
the DMAC_DPIPx register for channel x.
ing to the DMAC_EBCISR register.
Table 31-3 on page
Linked List item.
is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN
register is enabled.
buffer of data (assuming non-memory peripherals). DMAC acknowledges at the com-
pletion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
register is written out to the same location on the same layer
(DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the
DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer
The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs)
setup up in memory, although fetched during a LLI fetch, are not used.
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register although fetched is
not used.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface
source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
Table
31-3.
483.
Figure 31-5 on page 482
Table 31-3 on page 483
shows a Linked List example with two
while the
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11