SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 498

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 31-13. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address
498
498
SAM9G35
SAM9G35
Address of
Source Layer
The transfer is similar to that shown in
The DMAC Transfer flow is shown in
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
SADDR
automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as
shown in
the channel number) then hardware does not stall until it detects a write to the buf-
fer transfer completed interrupt enable register but starts the next buffer transfer
immediately. In this case software must clear the automatic mode bit,
DMAC_CTRLBx.AUTO, to put the device into ROW 1 of
before the last buffer of the DMAC transfer has completed.
Source Buffers
Table 31-3 on page
Figure 31-14 on page
Buffer0
Buffer2
Buffer1
Figure 31-13 on page
483.
Destination Buffers
DADDR(0)
DADDR(1)
DADDR(2)
Destination Layer
499.
Address of
498.
Table 31-3 on page 483
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11