SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 501

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 31-15. DMAC Transfer with Linked List Source Address and Contiguous Destination Address
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Source Layer
Address of
SADDR(1)
SADDR(0)
SADDR(2)
Note:
The DMAC transfer might look like that shown in
nation address is decrementing.
The DMAC transfer flow is shown in
18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and
the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx
register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
fetches the next LLI from the memory location pointed to by current DMAC_DSCRx
register and automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register
is left unchanged. The DMAC transfer continues until the DMAC samples the
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transfer match that described in Row 1 of
knows that the previous buffer transferred was the last buffer in the DMAC transfer.
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is
asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared
at the start of the transfer.
Source Buffers
Buffer 1
Buffer 0
Buffer 2
Figure 31-16 on page
Destination Buffers
Buffer 2
Buffer 1
Buffer 0
Table 31-3 on page
Figure 31-15 on page 501
502.
DADDR(2)
DADDR(1)
DADDR(0)
Destination Layer
483. The DMAC then
Address of
Note that the desti-
SAM9G35
SAM9G35
501
501