SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 505
SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Write Protection Registers
To prevent any single software error that may corrupt DMAC behavior, the DMAC address
space can be write-protected by setting the WPEN bit in the
ter”
If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the
DMAC Write Protect Status Register (MCI_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with
the appropriate access key, WPKEY.
The protected registers are:
•
•
•
•
•
•
•
•
•
•
“DMAC Global Configuration Register” on page 507
“DMAC Enable Register” on page 508
“DMAC Channel x [x = 0..7] Source Address Register” on page 518
“DMAC Channel x [x = 0..7] Destination Address Register” on page 519
“DMAC Channel x [x = 0..7] Descriptor Address Register” on page 520
“DMAC Channel x [x = 0..7] Control A Register” on page 521
“DMAC Channel x [x = 0..7] Control B Register” on page 523
“DMAC Channel x [x = 0..7] Configuration Register” on page 525
“DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register” on page 527
“DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register” on page
528
(DMAC_WPMR).
“DMAC Write Protect Mode Regis-
SAM9G35
SAM9G35
505
505
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