SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 534

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

32.4
32.4.1
32.4.2
534
534
Product Dependencies
SAM9G35
SAM9G35
I/O Lines
Power Management
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard
product does not dedicate pads to external over current protection.
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The
embedded USB High Speed physical transceivers are controlled by the USB host controller.
One transceiver is shared with the USB High Speed Device. In this case USB Host High Speed
Controller uses only Port B, i.e., the signals HFSDPB, HFSDMB, HHSDPB and HHSDMB.
The port A is driven by the USB High Speed Device, the output signals are DFSDP, DFSDM,
DHSDP and DHSDM.
The transceiver is automatically selected for Device operation once the USB High Speed Device
is enabled.
One transceiver is shared with USB Device High Speed. In this case USB Host High Speed
Controller uses only Port A, i.e., the signals HFSDPA, HFSDMA, HHSDPA and HHSDMA.
The port B is driven by the USB Device High Speed, the output signals are DFSDP, DFSDM,
DHSDP and DHSDM.
The transceiver is automatically selected for Device operation once the USB Device High Speed
is enabled.
The USB Host High Speed requires a 48 MHz clock for the embedded High-speed transceivers.
This clock is provided by the UTMI PLL, it is UPLLCK.
In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not
possible. Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as
the input clock of OHCI.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations.
These clocks must be generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV
field.
Thus the USB Host peripheral receives three clocks from the Power Management Controller
(PMC): the Peripheral Clock (MCK domain), the UHP48M and the UHP12M (built-in UHP48M
divided by four) used by the OHCI to interface with the bus USB signals (Recovered 12 MHz
domain) in Full-speed operations.
For High-speed operations, the user has to perform the following:
• Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER register.
• Write CKGR_PLLCOUNT field in PMC_UCKR register.
• Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
• Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
• Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11