SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 695

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

35.8.11
Name:
Address:
Access:
• SPIWPVS: SPI Write Protection Violation Status
• SPIWPVSRC: SPI Write Protection Violation Source
This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx)
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
31
23
15
–
–
7
–
SPIWPVS value
SPI Write Protection Status Register
0x1
0x2
0x3
0x4
0x5
0x6
0x7
30
22
14
SPI_WPSR
0xF00000E8 (0), 0xF00040E8 (1)
Read-only
–
–
6
–
The Write Protection has blocked a Write access to a protected register (since the last read).
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx).
Both Write Protection violation and software reset with Write Protection enabled have occurred
since the last read.
Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
The Write Protection has blocked a Write access to a protected register and write accesses have
been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select
“i” was active) since the last read.
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx) and some write
accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while
the Chip Select “i” was active) since the last read.
- The Write Protection has blocked a Write access to a protected register.
and
- Software Reset has been performed while Write Protection was enabled.
and
- Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
29
21
13
–
–
5
–
28
20
12
–
–
4
–
SPIWPVSRC
27
19
11
–
–
3
–
Violation Type
26
18
10
–
–
2
SPIWPVS
25
17
–
–
9
1
SAM9G35
SAM9G35
24
16
–
–
8
0
695
695