SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 744

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.7
Table 37-4.
Notes:
744
744
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20 - 0xFC
0x100 - 0x1FC
0x200 + ch_num * 0x20 + 0x00
0x200 + ch_num * 0x20 + 0x04
0x200 + ch_num * 0x20 + 0x08
0x200 + ch_num * 0x20 + 0x0C
0x200 + ch_num * 0x20 + 0x10
Pulse Width Modulation Controller (PWM) User Interface
1. Some registers are indexed with “ch_num” index ranging from 0 to 3.
SAM9G35
SAM9G35
Register Mapping
(1)
Register
PWM Mode Register
PWM Enable Register
PWM Disable Register
PWM Status Register
PWM Interrupt Enable Register
PWM Interrupt Disable Register
PWM Interrupt Mask Register
PWM Interrupt Status Register
Reserved
Reserved
PWM Channel Mode Register
PWM Channel Duty Cycle Register
PWM Channel Period Register
PWM Channel Counter Register
PWM Channel Update Register
Name
PWM_MR
PWM_ENA
PWM_DIS
PWM_SR
PWM_IER
PWM_IDR
PWM_IMR
PWM_ISR
PWM_CMR
PWM_CDTY
PWM_CPRD
PWM_CCNT
PWM_CUPD
–
Read-write
Read-write
Read-write
Read-write
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-only
Write-only
Access
–
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Reset
0x0
0x0
0x0
0x0
0
0
0
0
–
-
-
-
-
-