SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 781

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Notes:
38.10.5.5
Figure 38-30. Repeated Start + Reversal from Read to Write Mode
Figure 38-31. Repeated Start + Reversal from Write to Read Mode
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
TWI_RHR
TWI_RHR
TWI_THR
TWI_THR
TXCOMP
TXCOMP
EOSACC
EOSACC
SVREAD
SVREAD
Reversal of Read to Write
Reversal of Write to Read
RXRDY
RXRDY
SVACC
SVACC
TXRDY
TXRDY
TWD
TWD
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
SADR.
nism is finished.
Reversal after a Repeated Start
S
S
As soon as a START is detected
As soon as a START is detected
SADR
SADR
The master initiates the communication by a read command and finishes it by a write command.
Figure 38-30 on page 781
1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
The master initiates the communication by a write command and finishes it by a read com-
mand.Figure 38-31 on page 781
mode.
W
R
Read TWI_RHR
A
A
DATA0
DATA0
DATA0
A
A
DATA0
DATA1
DATA1
DATA1
describes the repeated start + reversal from Read to Write mode.
NA
A
describes the repeated start + reversal from Write to Read
DATA1
Sr
Sr
SADR
SADR
Cleared after read
Cleared after read
R
W
DATA2
A
A
DATA2
DATA2
DATA2
A
A
DATA3
DATA3
DATA3
SAM9G35
SAM9G35
DATA3
NA
A
P
P
781
781