SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 926

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.7.10
926
SAM9G35
Buffer Structure
To complete the circuit, a programmable debouncer is placed at the output of the Schmitt trig-
ger. This debouncer is programmable up to 2
be selected by programming the field PENDBC in “ADC Touchscreen Mode Register”.
Due to the analog switch’s structure, the debouncer circuitry is only active when no conversion
(Touchscreen or classic ADC channels) is in progress. Thus, if the time between the end of a
conversion sequence and the arrival of the next trigger event is lower than the debouncing time
configured on PENDBC, the debouncer will not detect any contact.
Figure 41-11. Touchscreen Pen Detect
The Touchscreen Pen Detect can be used to generate an ADC interrupt to wake up the system.
The Pen Detect generates two types of status, reported in the “ADC Interrupt Status Register”:
Both bits are automatically cleared as soon as the Status Register (ADC_SR) is read, and can
generate an interrupt by writing the “ADC Interrupt Enable Register”.
Moreover, the rising of either one of them clears the other, they cannot be set at the same time.
The PENS bit of the ADC_SR indicates the current status of the pen contact.
The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The
same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event
occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1,
ADC_SEQR2, ADC_TSMR) the structure differs. Each data transferred to DMA buffer, carried
• the PEN bit is set as soon as a contact exceeds the debouncing time as defined by PENDBC
• the NOPEN bit is set as soon as no current flows for a time over the debouncing time as
and remains set until ADC_SR is read.
defined by PENDBC and remains set until ADC_SR is read.
Y-/SENSE
X+/U
X-/U
Y+/L
L
R
R
L
L
VDDANA
VDDANA
VDDANA
GND
GND
GND
GND
GND
2
4
0
3
1
15
ADC clock periods. The debouncer length can
To the ADC
Debouncer
PENDBC
11053B–ATARM–22-Sep-11
Pen Interrupt