SAM9G35 Atmel Corporation, SAM9G35 Datasheet - Page 241
SAM9G35
Manufacturer Part Number
SAM9G35
Description
Manufacturer
Atmel Corporation
Specifications of SAM9G35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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TAP
TCM
Test Access Port (TAP)
Thumb instruction
Thumb state
Tightly coupled memory (TCM)
TLB
Translation Lookaside Buffer (TLB)
Translation table
Translation table walk
Undefined
Unpredictable
ARM DDI0198D
See Test access port.
See Tightly coupled memory.
The collection of four mandatory and one optional terminals that form the input/output
and control interface to a JTAG boundary-scan architecture. The mandatory terminals
are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is
mandatory in ARM cores because it is used to reset the debug logic.
A halfword that specifies an operation for an ARM processor in Thumb state to
perform. Thumb instructions must be halfword-aligned.
A processor that is executing Thumb (16-bit) halfword aligned instructions is operating
in Thumb state.
An area of low latency memory that provides predictable instruction execution or data
load timing in cases where deterministic performance is required. TCMs are suited to
holding:
- critical routines (such as for interrupt handling)
- scratchpad data
- data types whose locality is not suited to caching
- critical data structures (such as interrupt stacks).
See Translation Look-aside Buffer.
A cache of recently used page table entries that avoid the overhead of page table
walking on every memory access. Part of the Memory Management Unit.
A table, held in memory, that contains data that defines the properties of memory areas
of various fixed sizes.
The process of doing a full translation table lookup. It is performed automatically by
hardware.
Indicates an instruction that generates an Undefined instruction trap. See the ARM
Architecture Reference Manual for more details on ARM exceptions.
Means that the behavior of the ETM cannot be relied upon. Such conditions have not
been validated. When applied to the programming of an event resource, only the output
of that event resource is Unpredictable.
Unpredictable behavior can affect the behavior of the entire system, because the ETM
is capable of causing the core to enter debug state, and external outputs may be used for
other purposes.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Glossary-17
Glossary
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