SAM9G45 Atmel Corporation, SAM9G45 Datasheet
SAM9G45
Specifications of SAM9G45
Related parts for SAM9G45
SAM9G45 Summary of contents
Page 1
... Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock • I/O – Five 32-bit Parallel Input/Output Controllers – 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package – 324-ball TFBGA, pitch 0.8 mm ® Processor AT91SAM ARM-based Embedded MPU SAM9G45 6438G–ATARM–19-Apr-11 ...
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... LCD Controller, resistive touch- screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the pro- cessor running at 400MHz and multiple 100+ Mbps data rate peripherals, the SAM9G45 has the performance and bandwidth to the network or local storage media to provide an adequate user experience ...
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... Block Diagram Figure 2-1. SAM9G45 Block Diagram 6438G–ATARM–19-Apr-11 PIO SAM9G45 3 ...
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... XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0 - PCK1 Programmable Clock Output SAM9G45 4 gives details on the signal names classified by peripheral. Active Type Level Power Supplies Power Power Power ...
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... Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE I/O I/O I/O SAM9G45 Reference Voltage Comments Driven at 0V only. 0: The device is in backup mode VDDBU 1: The device is running (not in backup mode). Accept between 0V and VDDBU VDDBU ...
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... Write Enable NBS0 - NBS3 Byte Mask Signal CFCE1 - CFCE2 CompactFlash Chip Enable CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write SAM9G45 6 Active Reference Type Level (1) I/O (1) I/O I/O VDDIOM0 Output VDDIOM0 Output ...
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... Low Output Low Output Output Output High Speed Multimedia Card Interface - HSMCIx I/O I/O I/O I/O Output Input Output Input Synchronous Serial Controller - SSCx Output Input I/O I/O I/O I/O SAM9G45 Reference Voltage Comments VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 (1) (1) (1) (1) (1) ...
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... USB Host Port B High Speed Data - DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + SAM9G45 8 Active Type Level AC97 Controller - AC97C Input Output Output Input ...
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... LCD Controller - LCDC Output Output Output Output Output Output Output Output Touch Screen Analog-to-Digital Converter Analog Analog Analog SAM9G45 Reference Voltage Comments (1) MII only, REFCK in RMII (1) MII only (1) (1) ETX0-ETX1 only in RMII (1) MII only (1) RXDV in MII, CRSDV in RMII ...
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... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. SAM9G45 10 Active Reference ...
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... Package and Pinout The SAM9G45 is delivered in a 324-ball TFBGA package. 4.1 Mechanical Overview of the 324-ball TFBGA Package Figure 4-1 Figure 4-1. 6438G–ATARM–19-Apr-11 shows the orientation of the 324-ball TFBGA Package Orientation of the 324-ball TFBGA Package ...
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... TFBGA Package Pinout Table 4-1. SAM9G45 Pinout for 324-ball BGA Package Pin Signal Name Pin A1 PC27 E10 A2 PC28 E11 A3 PC25 E12 A4 PC20 E13 A5 PC12 E14 A6 PC7 E15 A7 PC5 E16 A8 PC0 E17 A9 NWR3/NBS3 E18 A10 NCS0 F1 A11 DQS0 F2 A12 RAS F3 A13 SDCK ...
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... Table 4-1. SAM9G45 Pinout for 324-ball BGA Package (Continued) Pin Signal Name Pin C13 D10 H4 C14 D6 H5 C15 D2 H6 C16 GNDIOM H7 C17 A18 H8 C18 A12 H9 D1 XOUT32 H10 D2 PD20 H11 D3 GNDBU H12 D4 VDDBU H13 D5 PC24 H14 D6 PC18 H15 D7 PC13 H16 D8 PC6 H17 ...
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... Power Considerations 5.1 Power Supplies The SAM9G45 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. • VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). • ...
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... Memories Figure 6-1. SAM9G45 Memory Mapping Address Memory Space 0x00000000 Internal Memories 0x10000000 EBI Chip Select 0 0x20000000 EBI Chip Select 1 DDRSDRC1 0x30000000 EBI Chip Select 2 0x40000000 EBI Chip Select 3 NANDFlash 0x50000000 EBI Chip Select 4 Compact Flash Slot 0 0x60000000 EBI Chip Select 5 Compact Flash Slot 1 ...
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... Internal SRAM The SAM9G45 product embeds a total of 64Kbytes high-speed SRAM split in 4 blocks of 16 KBytes connected to one slave of the matrix. After reset and until the Remap Command is per- formed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. After Remap, the SRAM also becomes available at address 0x0 ...
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... AHB 6.2.3 Internal ROM The SAM9G45 embeds an Internal ROM, which contains the boot ROM and SAM-BA At any time, the ROM is mapped at address 0x0040 0000 also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command. I/O Drive Selection and Delay Control 6 ...
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... D[14] <=> DELAY2[27:24], – D[15] <=> DELAY2[31:28] D[31,16]on PIOC[31:16] controlled by 2 registers, DELAY3 and DELAY4, located in the HSMC3 user interface – D[16] <=> DELAY3[3:0], – D[17] <=> DELAY3[7:4],..., – D[22] <=> DELAY3[27:24], – PC[23] <=> DELAY3[31:28] – D[24] <=> DELAY4[3:0], – D[25] <=> DELAY4[7:4],..., SAM9G45 18 6438G–ATARM–19-Apr-11 ...
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... PA[30:23]. The delay is controlled by 2 registers, DELAY1 and DELAY2, located in the PIOA user interface. – PA[2] <=> DELAY1[3:0], – PA[3] <=> DELAY1[7:4],..., – PA[8] <=> DELAY1[27:24], – PA[9] <=> DELAY1[31:28] – PA[23] <=> DELAY2[3:0], – PA[24] <=> DELAY2[7:4],..., – PA[29] <=> DELAY2[27:24], – PA[30] <=> DELAY2[31:28] 6438G–ATARM–19-Apr-11 SAM9G45 19 ...
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... All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 7-1 on page 21 Figure 6-1 on page 15 peripherals. SAM9G45 20 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6438G–ATARM–19-Apr-11 ...
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... System Controller Block Diagram Figure 7-1. SAM9G45 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT ...
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... Chip Identification The AT91SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. • Chip ID: 0x819B05A2 • Ext ID: 0x00000004 • JTAG ID: 05B2_703F • ARM926 TAP ID: 0x0792603F 7.4 Backup Section The SAM9G45 features a Backup Section that embeds: • RC Oscillator • ...
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... Reserved 31 AIC 6438G–ATARM–19-Apr-11 Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G45. A peripheral identifier is required Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D/E ...
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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 8.4 Peripheral Signals Multiplexing on I/O Lines The SAM9G45 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multi- plexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... ETX3 I/O VDDIOP0 ERX2 I/O VDDIOP0 ERX3 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 SCK3 I/O VDDIOP0 RTS3 I/O VDDIOP0 CTS3 I/O VDDIOP0 PWM3 I/O VDDIOP0 TIOB2 I/O VDDIOP0 ETXER I/O VDDIOP0 ERXCK I/O VDDIOP0 ECRS I/O VDDIOP0 ECOL I/O VDDIOP0 PCK0 I/O VDDIOP0 SAM9G45 Function Comments 25 ...
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... TXD0 PB20 ISI_D0 PB21 ISI_D1 PB22 ISI_D2 PB23 ISI_D3 PB24 ISI_D4 PB25 ISI_D5 PB26 ISI_D6 PB27 ISI_D7 PB28 ISI_PCK PB29 ISI_VSYNC PB30 ISI_HSYNC PB31 ISI_MCK SAM9G45 26 Reset Power Peripheral B State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ISI_D8 I/O VDDIOP2 ...
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... A20 VDDIOM1 A21 VDDIOM1 A22 VDDIOM1 A23 VDDIOM1 A24 VDDIOM1 I/O VDDIOM1 RTS2 I/O VDDIOM1 TCLK2 I/O VDDIOM1 CTS2 I/O VDDIOM1 A25 VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 SAM9G45 Function Comments 27 ...
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... SPI1_NPCS3 PD20 TIOA0 PD21 TIOA1 PD22 TIOA2 PD23 TCLK0 PD24 SPI0_NPCS1 PD25 SPI0_NPCS2 PD26 PCK0 PD27 PCK1 PD28 TSADTRG PD29 TCLK1 TIOB0 PD30 PD31 TIOB1 SAM9G45 28 Reset Power Peripheral B State Supply PWM3 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 TIOA5 I/O VDDIOP0 ...
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... LCDD5 I/O VDDIOP1 LCDD6 I/O VDDIOP1 LCDD7 I/O VDDIOP1 LCDD10 I/O VDDIOP1 LCDD11 I/O VDDIOP1 LCDD12 I/O VDDIOP1 LCDD13 I/O VDDIOP1 LCDD14 I/O VDDIOP1 LCDD15 I/O VDDIOP1 LCDD18 I/O VDDIOP1 LCDD19 I/O VDDIOP1 LCDD20 I/O VDDIOP1 LCDD21 I/O VDDIOP1 LCDD22 I/O VDDIOP1 LCDD23 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 PCK1 I/O VDDIOP1 SAM9G45 Function Comments 29 ...
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... SAM9G45 30 6438G–ATARM–19-Apr-11 ...
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... The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S integer core • a Memory Management Unit (MMU) • separate instruction and data AMBA AHB bus interfaces • separate instruction and data TCM interfaces 6438G–ATARM–19-Apr-11 ™ processor is a member of the ARM9 SAM9G45 ™ family of general-purpose micropro- 31 ...
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... Separate Masters for both instruction and data access providing complete Matrix – Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit • TCM Interface SAM9G45 32 each quarter of the page system flexibility ...
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... External Coprocessor Interface ARM9EJ-S Processor Core Read Data Data Instruction Address MMU Instruction Data TLB TLB Data Address AHB Interface and Write Buffer AMBA AHB SAM9G45 ETM9 Trace Port Interface Instruction Fetches Address ITCM Interface Instruction TCM Instruction Address Instruction Cache 33 ...
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... ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. SAM9G45 34 6438G–ATARM–19-Apr-11 ...
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... ARM9TDMI Modes and Registers Layout Supervisor Mode Abort Mode R10 R10 R11 R11 SAM9G45 Undefined Interrupt Fast Interrupt Mode Mode R8_FIQ R9 R9 R9_FIQ ...
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... For more details, refer to ARM Software Development Kit. The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC SAM9G45 36 ARM9TDMI Modes and Registers Layout Supervisor Mode Abort Mode R12 ...
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... Status Register Format Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than shows the status register format, where: SAM9G45 Mode Mode bits Thumb state bit FIQ disable IRQ disable 37 ...
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... The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the SAM9G45 38 into LR (current PC(r15 depending on the exception). ...
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... Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register B Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte SAM9G45 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry RSC Reverse Subtract with Carry ...
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... The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions SAM9G45 40 ARM Instruction Mnemonic List (Continued) Operation Load Half Word Load Byte ...
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... Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch SAM9G45 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry CMN Compare Negated ...
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... ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 9-5. Register Notes: SAM9G45 42 CP15 Registers Name ( Code (1) 0 Cache type ...
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... Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. 6438G–ATARM–19-Apr-11 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 SAM9G45 CRn CRm ...
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... Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- SAM9G45 44 Mapping Details Mapping Size Access Permission By ...
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... The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 6438G–ATARM–19-Apr-11 SAM9G45 45 ...
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... Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the SAM9G45 46 6438G–ATARM–19-Apr-11 ...
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... When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 6438G–ATARM–19-Apr-11 SAM9G45 47 ...
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... However, the base address of a TCM must be aligned to its size, and the DTCM and ITCM regions must not overlap. TCM mapping is per- formed by using TCM region register (register 9) in CP15. The user should input the right mapping address for TCMs. SAM9G45 48 6438G–ATARM–19-Apr-11 ...
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... NCB, WT that has missed in DCache) • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT write. Full-line cache write-back, eight-word burst NCNB, NCB, WT write. Cache linefill SAM9G45 49 ...
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... SAM9G45 50 6438G–ATARM–19-Apr-11 ...
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... SAM9G45 Debug and Test 10.1 Description The SAM9G45 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica- tion Channel ...
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... Block Diagram Figure 10-1. Debug and Test Block Diagram TAP: Test Access Port SAM9G45 52 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD DRXD 6438G–ATARM–19-Apr-11 ...
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... Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2. Application Debug and Trace Environment Example 6438G–ATARM–19-Apr-11 shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG Interface ICE/JTAG Connector RS232 SAM9G45 Connector SAM9G45-based Application Board SAM9G45 Host Debugger PC Terminal 53 ...
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... Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n SAM9G45 SAM9G45-based Application Board In Test Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Reset Signal Test Clock ...
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... TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 6438G–ATARM–19-Apr-11 ™ is supported via the ICE/JTAG port connected to a SAM9G45 55 ...
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... A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM9G45 Debug Unit Chip ID value is 0x819B 05A2 and the extended ID is 0x00000004 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. ...
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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The SAM9G45 manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. ...
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... Flow Diagram The Boot Program implements the algorithm shown below in Figure 11-1. Boot Program Algorithm Flow Diagram SAM9G45 58 Device S etup Y es Valid boot code Copy and run it found in one in internal NVM No S AM-BA Monitor Figure 11-1. 6438G–ATARM–19-Apr-11 ...
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... C variable initialization: non zero-initialized data are initialized in RAM (copy from ROM to RAM). Zero-initialized data are set RAM. 6. PLLA initialization: PLLA is configured to allow communication on the USB link for the SAM-BA Monitor. Its configuration depends on the Main Oscillator source (external clock or crystal) and on its frequency. 6438G–ATARM–19-Apr-11 SAM9G45 59 ...
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... NVM Boot 11.4.1 NVM Bootloader Program Description Figure 11-2. NVM bootloader program diagram SAM9G45 60 Start Initialize NVM No Initialization Valid code detection in NVM No NVM contains valid code Y es Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. ...
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... Figure 11-4. LDR Opcode 6438G–ATARM–19-Apr-11 0x0000_0000 Internal ROM 0x0030_0000 Internal SRAM 0x0040_0000 Internal ROM SAM9G45 0x0000_0000 REMAP Internal SRAM 0x0030_0000 Internal SRAM 0x0040_0000 Internal ROM set 61 ...
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... Example An example of valid vectors follows 11.4.2.2 boot.bin file check The NVM bootloader program looks for a boot.bin file in the root directory of a FAT12/16/32 for- matted NVM Flash. SAM9G45 Size of the code to download in bytes ea000006 B 0x20 ...
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... Yes Copy from NAND Flash to SRAM Yes Copy from SD Card to SRAM Yes Copy from SPI Flash to SRAM Yes Copy from TWI EEPROM to SRAM SAM9G45 NAND Flash Bootloader Run SD Card Bootloader Run SPI Flash Bootloader Run TWI EEPROM Bootloader Run Table 11-1 ...
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... The SD Card bootloader uses MCI0. It uses only one valid code detection. It searches a boot.bin file. Supported SD Card devices SD Card Boot supports all SD Card memories compliant with SD Memory Card Specification V2.0. This includes SDHC cards. SAM9G45 64 Supported SLC Small Block NAND Flash Size PageSize ...
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... Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits 2 C-compatible TWI EEPROM memories using 7 bits device contains a list of pins that are driven during the boot program execution. These pins SAM9G45 Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 4096 ...
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... Initialize DBGU and USB – Check if USB Device enumeration has occurred. – Check if characters have been received on the DBGU. – Once the communication interface is identified, the application runs in an infinite SAM9G45 66 PIO Driven during Boot Program Execution Peripheral EBI CS3 SMC ...
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... Address, Value# read a half word Address,# write a word Address, Value# read a word Address,# send a file Address,# receive a file Address, NbOfBytes# go Address# display version No argument SAM9G45 on DBGU ? Y es Run monitor on the DBGU link Example N# T# O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# ...
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... SAM9G45 68 There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. ...
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... Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK ® ® , from Windows 98SE to Windows XP SAM9G45 Device ® . The CDC document, available at 69 ...
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... Endpoint 64-byte Bulk OUT endpoint and endpoint 64-byte Bulk IN endpoint. SAM- BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. SAM9G45 70 Handled Standard Requests Definition Returns the current device configuration value ...
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... The configuration of the Reset Controller is saved as supplied on VDDBU. 12.3 Block Diagram Figure 12-1. Reset Controller Block Diagram Main Supply POR Backup Supply POR NRST WDRPROC wd_fault 6438G–ATARM–19-Apr-11 Reset Controller Startup Counter Reset State Manager user_reset NRST Manager nrst_out exter_nreset SLCK SAM9G45 rstc_irq proc_nreset periph_nreset backup_neset 71 ...
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... The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN RSTC_MR disables the User Reset trigger. SAM9G45 72 Figure 12-2 shows the block diagram of the NRST Manager. ...
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... Startup Counter, which operates at Slow Clock. The pur- pose of this counter is to make sure the Slow Clock oscillator is stable before starting up the 6438G–ATARM–19-Apr-11 Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs XXX BMS sampling delay = 3 cycles SAM9G45 ...
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... SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) SAM9G45 74 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles Any Freq. 0x0 = General Reset ...
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... The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 6438G–ATARM–19-Apr-11 Resynch. Processor Startup 2 cycles = 3 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) SAM9G45 Any Freq. 0x1 = WakeUp Reset XXX 75 ...
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... ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these com- mands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. SAM9G45 Resynch ...
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... ERSTL. However, the resulting low level on NRST does not result in a User Reset state. 6438G–ATARM–19-Apr-11 Any Freq. Resynch. Processor Startup 1 cycle = 3 cycles XXX Any EXTERNAL RESET LENGTH SAM9G45 0x3 = Software Reset 8 cycles (ERSTL=2) 77 ...
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... A watchdog event is impossible because the Watchdog Timer is being reset by the – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. SAM9G45 78 Any Freq. Processor Startup ...
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... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 12-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 6438G–ATARM–19-Apr-11 SAM9G45 read RSTC_SR 2 cycle resynchronization Figure 79 ...
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... Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. SAM9G45 80 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset Backup Reset ...
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... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6438G–ATARM–19-Apr- KEY – – – – – – – – EXTRST SAM9G45 – – – PERRST – PROCRST 24 16 – 8 – ...
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... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. SAM9G45 – ...
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... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6438G–ATARM–19-Apr- KEY – – – – – URSTIEN – SAM9G45 – – ERSTL – – URSTEN (ERSTL+1) Slow Clock cycles. This 83 ...
Page 84
... SAM9G45 84 6438G–ATARM–19-Apr-11 ...
Page 85
... Slow Clock is 32.768 kHz). The 32-bit counter can count sponding to more than 136 years, then roll over to 0. 6438G–ATARM–19-Apr-11 Controller 0 RTT_SR 1 0 32-bit Counter RTT_SR CRTV RTT_SR ALMV RTT_MR RTTINCIEN set RTTINC reset read RTT_MR ALMIEN reset ALMS set = SAM9G45 rtt_int rtt_alarm 32 seconds, corre- 85 ...
Page 86
... Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: SAM9G45 86 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register ...
Page 87
... Figure 13-2. RTT Counting SCLK RTPRES - 1 Prescaler 0 RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface 6438G–ATARM–19-Apr-11 APB cycle ... 0 ALMV-1 ALMV SAM9G45 APB cycle ALMV+1 ALMV+2 ALMV+3 read RTT_SR 87 ...
Page 88
... Real-time Timer (RTT) User Interface Table 13-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register SAM9G45 88 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 6438G–ATARM–19-Apr-11 ...
Page 89
... Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 6438G–ATARM–19-Apr- – – – – – – RTPRES RTPRES 16 . SAM9G45 – – RTTRST RTTINCIEN ALMIEN – ...
Page 90
... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 13.5.3 Real-time Timer Value Register Register Name: RTT_VR Address: 0xFFFFFD28 Access Type: Read-only • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. SAM9G45 ALMV ALMV ALMV ALMV 29 ...
Page 91
... The Real-time Timer has been incremented since the last read of the RTT_SR. 6438G–ATARM–19-Apr- – – – – – – – – – – – – SAM9G45 – – – – – – – – – – RTTINC ALMS 91 ...
Page 92
... SAM9G45 92 6438G–ATARM–19-Apr-11 ...
Page 93
... Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 14.3 Block Diagram Figure 14-1. RTC Block Diagram Crystal Oscillator: SLCK Bus Interface 6438G–ATARM–19-Apr-11 32768 Divider Time Bus Interface Entry Control SAM9G45 Date Interrupt RTC Interrupt Control 93 ...
Page 94
... Each of these fields can be enabled or disabled to match the alarm condition: • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled given month, date, hour/minute/second. • If only the “seconds” field is enabled, then an alarm is generated every minute. SAM9G45 94 6438G–ATARM–19-Apr-11 ...
Page 95
... If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro- grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. SAM9G45 95 ...
Page 96
... Figure 14-2. Update Sequence Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL Clear ACKUPD bit in RTC_SCCR Update Time andor Calendar values in Clear UPDTIM and/or UPDCAL bit in SAM9G45 96 Begin bit(s) in RTC_CR Read RTC_SR No ACKUPD = 1 ? Yes RTC_TIMR/RTC_CALR RTC_CR End Polling or IRQ (if enabled) 6438G–ATARM–19-Apr-11 ...
Page 97
... Name Access RTC_CR Read-write RTC_MR Read-write RTC_TIMR Read-write RTC_CALR Read-write RTC_TIMALR Read-write RTC_CALALR Read-write RTC_SR Read-only RTC_SCCR Write-only RTC_IER Write-only RTC_IDR Write-only RTC_IMR Read-only RTC_VER Read-only SAM9G45 Reset 0x0 0x0 0x0 0x01819819 0x0 0x01010000 0x0 --- --- --- 0x0 0x0 97 ...
Page 98
... Every day at noon. • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Week change (every Monday at time 00:00:00 Month change (every 01 of each month at time 00:00:00 Year change (every January 1 at time 00:00:00). SAM9G45 – ...
Page 99
... All non-significant bits read zero. 6438G–ATARM–19-Apr- – – – – – – – – – – – – SAM9G45 – – – – – – – – – – – HRMOD 99 ...
Page 100
... HOUR: Current Hour The range that can be set (BCD) in 12-hour mode (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. SAM9G45 100 – – ...
Page 101
... The range that can be set (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 6438G–ATARM–19-Apr- YEAR CENT SAM9G45 26 25 DATE 18 17 MONTH 101 ...
Page 102
... This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. SAM9G45 102 – – ...
Page 103
... DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled The date-matching alarm is enabled. 6438G–ATARM–19-Apr- – – – – – – – SAM9G45 26 25 DATE 18 17 MONTH 10 9 – – – – – 0 – 103 ...
Page 104
... No calendar event has occurred since the last clear least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. SAM9G45 104 – ...
Page 105
... Clears corresponding status flag in the Status Register (RTC_SR). 6438G–ATARM–19-Apr- – – – – – – – – – – CALCLR TIMCLR SAM9G45 26 25 – – – – – – SECCLR ALRCLR ACKCLR 24 – 16 – 8 – 0 105 ...
Page 106
... No effect The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable effect The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable effect. • The selected calendar event interrupt is enabled. SAM9G45 106 – – – ...
Page 107
... The selected calendar event interrupt is disabled. 6438G–ATARM–19-Apr- – – – – – – – – – – CALDIS TIMDIS SAM9G45 – – – – – – SECDIS ALRDIS ACKDIS – – 8 – 0 107 ...
Page 108
... TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled The selected calendar event interrupt is enabled. SAM9G45 108 – – ...
Page 109
... RTC_CALALR has contained invalid data since it was last programmed. 6438G–ATARM–19-Apr- – – – – – – – – – – – NVCALALR SAM9G45 26 25 – – – – – – NVTIMALR NVCAL NVTIM 24 – 16 – 8 – 0 109 ...
Page 110
... SAM9G45 110 6438G–ATARM–19-Apr-11 ...
Page 111
... The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. 6438G–ATARM–19-Apr-11 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR SAM9G45 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR ...
Page 112
... PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface SAM9G45 112 APB cycle MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR Figure 15-2 APB cycle ...
Page 113
... Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register 6438G–ATARM–19-Apr-11 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only SAM9G45 Reset 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 113 ...
Page 114
... PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. SAM9G45 114 – ...
Page 115
... PICNT CPIV CPIV SAM9G45 – – – – – – – – – – – PITS CPIV ...
Page 116
... Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 6438G–ATARM–19-Apr- PICNT CPIV CPIV SAM9G45 CPIV 116 ...
Page 117
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6438G–ATARM–19-Apr-11 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset SAM9G45 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 117 ...
Page 118
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. SAM9G45 118 6438G–ATARM–19-Apr-11 ...
Page 119
... Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6438G–ATARM–19-Apr-11 Watchdog Error WDT_CR = WDRSTT SAM9G45 Watchdog Underflow if WDRSTEN WDRSTEN is 0 119 ...
Page 120
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G45 120 Name WDT_CR WDT_MR WDT_SR KEY – ...
Page 121
... The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6438G–ATARM–19-Apr- WDDBGHLT WDD WDFIEN WDV SAM9G45 WDD WDV 121 ...
Page 122
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. SAM9G45 122 – ...
Page 123
... Figure 17-1. Shutdown Controller Block Diagram Shutdown Controller SHDW_MR CPTWK0 WKMODE0 WKUP0 RTTWKEN RTT Alarm 6438G–ATARM–19-Apr-11 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset SHDW_MR RTTWK SHDW_SR set SAM9G45 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW 123 ...
Page 124
... WKUP0 Wake-up 0 input SHDN Shutdown output 17.5 Product Dependencies 17.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller. SAM9G45 124 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset SHDW_MR ...
Page 125
... SHDW_SR. When using the RTC alarm to wake up the system, the user must ensure that the RTC alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail. 6438G–ATARM–19-Apr-11 SAM9G45 125 ...
Page 126
... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G45 126 Name SHDW_CR SHDW_MR SHDW_SR KEY 21 ...
Page 127
... None. No detection is performed on the wake-up input Low to high level High to low level Both levels change SHDN pin. SHDN pin – – – – – RTCWKEN 10 9 – – – – WKMODE0 SHDN pin is released SAM9G45 24 – 16 RTTWKEN 8 – 0 127 ...
Page 128
... At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. • RTCWK: Real-time Clock Wake- wake-up alarm from the RTC occurred since the last read of SHDW_SR least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. SAM9G45 128 – ...
Page 129
... Four 32-bit general-purpose backup registers 18.3 General Purpose Backup Registers (GPBR) User Interface Table 18-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0xc General Purpose Backup Register 3 6438G–ATARM–19-Apr-11 Name SYS_GPBR0 ... SYS_GPBR3 SAM9G45 Access Reset Read-write – ... ... Read-write – 129 ...
Page 130
... General Purpose Backup Register x Name: SYS_GPBRx Addresses: 0xFFFFFD60 [0], 0xFFFFFD64 [1], 0xFFFFFD68 [2], 0xFFFFFD6C [3] Type: Read-write • GPBR_VALUEx: Value of GPBR x SAM9G45 130 GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx 6438G–ATARM–19-Apr-11 ...
Page 131
... Allows Handling of Dynamic Exception Vectors 19.2.1 Matrix Masters The Bus Matrix of the SAM9G45 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. 6438G– ...
Page 132
... The four DDR ports are connected differently according to the application device. The user can disable the DDR multi-port in the DDR multi-port Register (bit DDRMP_DIS) in the Chip Configuration User Interface. SAM9G45 132 List of Bus Matrix Masters ™ ...
Page 133
... DDR_S1 ARM D DDRMP_DIS DDR_S2 DDR_S3 ISI LCD Ethernet USB DMA DMA MAC Device SAM9G45 10 11 USB Host EHCI Reserved 133 ...
Page 134
... Special Bus Granting Mechanism The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first access of a burst or single SAM9G45 134 & 5 ...
Page 135
... Every request attempted by this fixed default master will not cause any arbi- tration latency whereas other non privileged masters will still get one latency cycle. This technique is useful for a master that mainly perform single accesses or short bursts with some Idle cycles in between. 6438G–ATARM–19-Apr-11 SAM9G45 Section 19.7.2 “Bus 143. 135 ...
Page 136
... Predicted end of burst is generated at each single transfer inside the INCR transfer. 3. 4-beat bursts: Predicted end of burst is generated at the end of each 4-beat boundary inside INCR transfer. SAM9G45 136 136. “Undefined Length Burst Arbitration” on Section 19.5.1 “Arbitration “Slot Cycle Limit Arbi- ...
Page 137
... Arbitration Priority Scheme The bus Matrix arbitration scheme is organized in priority pools. Round-Robin priority is used inside the highest and lowest priority pools, whereas fix level prior- ity is used between priority pools and inside the intermediate priority pools. 6438G–ATARM–19-Apr-11 SAM9G45 137 ...
Page 138
... If two or more master requests are active at the same time inside the priority pool, they are serviced in a round-robin increasing master number order. SAM9G45 138 6438G–ATARM–19-Apr-11 ...
Page 139
... The protected registers are: “Bus Matrix Master Configuration Registers” “Bus Matrix Slave Configuration Registers” “Bus Matrix Priority Registers A For Slaves” “Bus Matrix Priority Registers B For Slaves” “Bus Matrix Master Remap Control Register” 6438G–ATARM–19-Apr-11 SAM9G45 139 ...
Page 140
... Priority Register A for Slave 4 0x00A4 Priority Register B for Slave 4 0x00A8 Priority Register A for Slave 5 0x00AC Priority Register B for Slave 5 0x00B0 Priority Register A for Slave 6 0x00B4 Priority Register B for Slave 6 SAM9G45 140 Name Access MATRIX_MCFG0 Read-write MATRIX_MCFG1 Read-write MATRIX_MCFG2 Read-write MATRIX_MCFG3 Read-write ...
Page 141
... Write Protect Mode Register 0x01E8 Write Protect Status Register 6438G–ATARM–19-Apr-11 Name Access MATRIX_PRAS7 Read-write MATRIX_PRBS7 Read-write – – MATRIX_MRCR Read-write – – – – MATRIX_WPMR Read-write MATRIX_WPSR Read-only SAM9G45 Reset 0x00000000 0x00000000 – 0x00000000 – – 0x00000000 0x00000000 141 ...
Page 142
... The undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end. 7: 128-beat Burst The undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end. Unless duly needed the ULBT should be let to its default 0 value for power saving. SAM9G45 142 – ...
Page 143
... DEFMSTR_TYPE to 0. 6438G–ATARM–19-Apr- – – – FIXED_DEFMSTR – – – SLOT_CYCLE “Write Protect Mode for details. SAM9G45 – – – DEFMSTR_TYPE – – SLOT_CYCLE Register”. 143 ...
Page 144
... All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-Robin arbitration is used inside the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used inside intermediate priority pools (MxPR = 1) and (MxPR = 2). See Section 19.5.2 “Arbitration Priority Scheme” SAM9G45 144 M7PR – ...
Page 145
... M9PR – “Write Protect Mode for details. SAM9G45 26 25 – – – – – M10PR 2 1 – M8PR Register”. 24 – 16 – 145 ...
Page 146
... RCB7 RCB6 This register can only be written if the WPEN bit is cleared in the • RCB: Remap Command Bit for Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master SAM9G45 146 – – ...
Page 147
... DDR Multi-Port Register 0x011C - 0x0124 Reserved 0x0128 EBI Chip Select Assignment Register 0x012C - 0x01FC Reserved 6438G–ATARM–19-Apr-11 Name Access CCFG_TCMR Read-write – – CCFG_DDRMPR Read-write – – CCFG_EBICSA Read-write – – SAM9G45 Reset 0x00000000 – 0x00000001 – 0x00010000 – 147 ...
Page 148
... Others: Reserved • DTCM_SIZE: Size of DTCM enabled memory block 000 (No DTCM Memory) 110 111 Others: Reserved • TCM_NWS: TCM Wait State 0: no TCM Wait State 1: 1 TCM Wait State (only for ration 3:1 or 4:1) SAM9G45 148 – – – 21 ...
Page 149
... Multi-Port is enabled 1: Multi-Port is disabled 6438G–ATARM–19-Apr- – – – – – – – – – – – – SAM9G45 – – – – – – – – – – – DDRMP_DIS 149 ...
Page 150
... This allows to avoid overshoots and give the best performances according to the bus load and external memories Low Drive, optimized for load capacitance < High Drive, optimized for load capacitance < 55 pF. Note: This concerns only stand-alone DDR controller. SAM9G45 150 – ...
Page 151
... Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 6438G–ATARM–19-Apr- WPKEY WPKEY WPKEY – – – Section 19.6 “Write Protect Registers” on page SAM9G45 – – WPEN 139. 151 ...
Page 152
... At least one Write Protect Violation has occurred since the last write of the MATRIX_WPMR. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the register address offset in which a write access has been attempted. Otherwise it reads as 0. SAM9G45 152 – ...
Page 153
... Port 2 Port 1 Port 0 EBI Bus Matrix DDRSDRC1 Compact Flash Controller NAND Flash Controller Static Memory Controller Section 22. ”DDR/SDR SDRAM Controller SAM9G45 DDR2 or LP-DDR Device DDR2 or LP-DDR or SDR or LP-SDR Device Compact Flash Device NAND Flash Device Static Memory Device (DDRSDRC)”. 153 ...
Page 154
... Self-refresh, Power-down and Deep Power Modes Supported • Power-up Initialization by Software • CAS Latency Supported • Reset function supported (DDR2) • Auto Precharge Command Not Used • On Die Termination not supported • OCD mode not supported SAM9G45 154 Average Latency of Transactions) 6438G–ATARM–19-Apr-11 ...
Page 155
... DDR2 Controller Block Diagram Figure 20-2. Organization of the DDR2 Bus Matrix AHB Address Decoders 6438G–ATARM–19-Apr-11 DDR2 DDR2 LPDDR Controller User Interface APB SAM9G45 DDR_A0-DDR_A13 DDR_D0-DDR_D15 DDR_CS DDR_CKE DDR_RAS, DDR_CAS DDR_CLK,#DDR_CLK DDR_DQS[0..1] DDR_DQM[0..1] DDR_WE DDR_BA0, DDR_BA1 DDR_VREF 155 ...
Page 156
... The pins used for interfacing the DDR2 memory are not multiplexed with the PIO lines. 20.1.6 Implementation Example The following hardware configuration is given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. SAM9G45 156 DDR2/LPDDR Controller Type Active Level ...
Page 157
... F7 E3 RAS VSS J1 VSS VSS A7 VSSQ B2 VSSQ G1 B8 RFU1 VSSQ L3 D2 RFU2 VSSQ L7 D8 RFU3 VSSQ E7 VSSDL SAM9G45 MN7 MN7 DDR_A0 DDR_D8 DQ0 DDR_A1 DDR_D9 DDR2 SDRAM DDR2 SDRAM DQ1 DDR_A2 DDR_D10 H7 D7 MT47H64M8CF-3 MT47H64M8CF-3 A2 DQ2 DDR_A3 DDR_D11 J2 ...
Page 158
... Memory Controllers. 20.2.2 Embedded Characteristics The SAM9G45 features an External Bus Interface to interface to a wide range of external mem- ories and to any parallel peripheral. 20.2.2.1 External Bus Interface • ...
Page 159
... Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 6438G–ATARM–19-Apr-11 Average Latency of Transactions) detected erroneous pages SAM9G45 159 ...
Page 160
... EBI Block Diagram Figure 20-3. Organization of the External Bus Interface Bus Matrix AHB Address Decoders SAM9G45 160 External Bus Interface DDR2 LPDDR SDRAM Controller MUX Static Logic Memory Controller CompactFlash Logic NAND Flash Logic ECC Controller Chip Select Assignor User Interface APB ...
Page 161
... Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported SDRAMC_A[12:11] Not Supported D[31:0] SAM9G45 Type Active Level I/O Output Input Output Output Output Output Output Output ...
Page 162
... NWRx enables corresponding byte x writes 0,1 NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. SAM9G45 162 details the connections to be applied between the EBI pins and the ...
Page 163
... WE WE IOR IOR IOW IOW CE1 CS0 CE2 CS1 – – – – – – – – – – SAM9G45 NAND Flash I/O0-I/O7 (4) I/O8-I/O15 – – – – – – – – – – – – – – ALE CLE – ...
Page 164
... For "CE don't care" NAND Flash devices, it can be either connected to NCS3/NANDCS or to any free PIO line. 4. I/O8 - !/O15 pins used only for 16-bit NANDFlash device. 5. EBI_NWAIT signal is multiplexed with PC15. 20.2.5.2 Connection Examples Figure 20-4 Figure 20-4. EBI Connections to Memory Devices SAM9G45 164 Pins of the Interfaced Device SDRAM CompactFlash DDRC SDRAMC ...
Page 165
... Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller section. 20.2.7.4 DDR2SDRAM Controller For information on the DDR2SDRAM Controller, refer to the DDR2SDRAMC section. 20.2.7.5 ECC Controller For information on the ECC Controller, refer to the ECC section. 6438G–ATARM–19-Apr-11 SAM9G45 165 ...
Page 166
... CF Address Space Note: Table 20-6. A[23:21] 000 010 100 110 111 SAM9G45 166 166. Offset 0x00E0 0000 Offset 0x00C0 0000 Offset 0x0080 0000 Offset 0x0040 0000 Offset 0x0000 0000 The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode) ...
Page 167
... Don’t 1 Access to Even Byte on D[7:0] Care 1 8 bits Access to Odd Byte on D[7:0] 1 – demonstrates a schematic representation of this logic. SAM9G45 to enable the required access type. SMC Access Mode Byte Select Byte Select Byte Select Byte Select Don’t Care – – Figure ...
Page 168
... EBI_CSA Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices. The EBI pins in corresponding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1). Table 20-9. Dedicated CompactFlash Interface Multiplexing Pins CS4A = 1 NCS4/CFCS0 CFCS0 NCS5/CFCS1 SAM9G45 168 CompactFlash Logic A23 A22 ...
Page 169
... NWAIT 6438G–ATARM–19-Apr-11 Access to CompactFlash Device CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW illustrates an example of a CompactFlash application. CFCS0 and DIR /OE /OE SAM9G45 Access to Other EBI Devices EBI Signals NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25 CompactFlash Connector D[15:0] _CD1 _CD2 A[10:0] _REG ...
Page 170
... NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 20-8. NAND Flash Application Example EBI PIO PIO SAM9G45 170 D[7:0] A[22:21] NCSx/NANDCS Not Connected NANDOE ...
Page 171
... Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Register located in the bus matrix memory space. • Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency. The DDR2 initialization sequence is described in the sub-section “DDR2 Device Initialization” of the DDRSDRC section. 6438G–ATARM–19-Apr-11 SAM9G45 171 ...
Page 172
... Register located in the bus matrix memory space. • Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency. The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Ini- tialization” in “DDR/SDR SDRAM Controller (DDRSDRC)”. SAM9G45 172 6438G–ATARM–19-Apr-11 ...
Page 173
... Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width programmed to 16 bits. The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”. 6438G–ATARM–19-Apr-11 SAM9G45 173 ...
Page 174
... The Data Bus Width programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”. SAM9G45 174 D0 2 DQ0 ...
Page 175
... U1 U1 K9F2G08U0M K9F2G08U0M D0 29 CLE I/ ALE R N.C 47 N.C 46 N.C N.C 45 N.C N.C 40 N.C N.C 39 N.C N.C 38 N.C PRE 35 N.C N.C 34 N.C N.C 33 N.C N.C 28 N.C N.C 27 N.C N.C N.C 37 N.C VCC 12 N.C VCC N.C N.C 36 N.C VSS 13 N.C VSS 100NF 100NF TSOP48 PACKAGE SAM9G45 3V3 C2 C2 100NF 100NF 175 ...
Page 176
... Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller. SAM9G45 176 10K ...
Page 177
... A17 A19 16 AT49BV6416 AT49BV6416 A18 A20 15 A19 A21 10 A20 A22 9 A21 12 RESET 3V3 VPP TSOP48 PACKAGE SAM9G45 D0 29 DQ0 D1 31 DQ1 D2 33 DQ2 D3 35 DQ3 D4 38 DQ4 D5 40 DQ5 D6 42 DQ6 D7 44 DQ7 D8 30 DQ8 D9 32 DQ9 ...
Page 178
... A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT Software Configuration The following configuration has to be performed: SAM9G45 178 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 ...
Page 179
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to CompactFlash timings and system bus frequency. 6438G–ATARM–19-Apr-11 SAM9G45 179 ...
Page 180
... A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT Software Configuration The following configuration has to be performed: SAM9G45 180 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 ...
Page 181
... The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode. The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode. 6438G–ATARM–19-Apr-11 SAM9G45 181 ...
Page 182
... SAM9G45 182 6438G–ATARM–19-Apr-11 ...
Page 183
... Write or Byte Select Access” on page 185 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page Byte-write or byte-select access, see Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 185 SAM9G45 Type Output Output Output Output Output ...
Page 184
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. SAM9G45 184 128K x 8 SRAM ...
Page 185
... This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6438G–ATARM–19-Apr-11 NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2. Figure 21-5 SAM9G45 Figure 21-2). NCS7 Memory Enable NCS6 Memory Enable NCS5 Memory Enable ...
Page 186
... Figure 21-3. Memory Connection for an 8-bit Data Bus Figure 21-4. Memory Connection for a 16-bit Data Bus Figure 21-5. Memory Connection for a 32-bit Data Bus SMC SAM9G45 186 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] D[31:16] D[15:0] A[20:2] NBS0 NBS1 NBS2 NBS3 NWE NRD NCS[2] ...
Page 187
... Byte Select Access is used to connect two 16-bit devices. Figure 21-7 mode, on NCS3 (BAT = Byte Select Access). 6438G–ATARM–19-Apr-11 Figure 21-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access SAM9G45 187 ...
Page 188
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. SAM9G45 188 D[7:0] D[15:8] ...
Page 189
... Bus 2x16-bit 4 x 8-bit Byte Select Byte Write NBS0 NWE NWR0 NBS1 NWR1 NBS2 NWR2 NBS3 NWR3 SAM9G45 D[15:0] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable ...
Page 190
... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. SAM9G45 190 Figure 21-8. NRD_SETUP NRD_PULSE ...
Page 191
... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 21.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 6438G–ATARM–19-Apr-11 SAM9G45 Figure 21-9). 191 ...
Page 192
... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. SAM9G45 192 NRD_PULSE NRD_PULSE ...
Page 193
... Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 6438G–ATARM–19-Apr-11 t PACC Data Sampling shows the typical read cycle of an LCD module. The read data is valid t t PACC Data Sampling SAM9G45 after PACC 193 ...
Page 194
... NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 21-12. Write Cycle MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NCS_WR_SETUP SAM9G45 194 NWE_SETUP NWE_PULSE NCS_WR_PULSE NWE_CYCLE Figure 21-12. The write cycle NWE_HOLD NCS_WR_HOLD 6438G–ATARM–19-Apr-11 ...
Page 195
... NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 21.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 6438G–ATARM–19-Apr-11 NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE SAM9G45 Figure 21-13). How- NWE_PULSE NCS_WR_PULSE NWE_CYCLE 195 ...
Page 196
... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. SAM9G45 196 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is shows the waveforms of a write operation with WRITE_MODE set to 0. The data is 6438G– ...
Page 197
... Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] gives the default value of timing parameters at reset. SAM9G45 Permitted Range Coded Value Effective Value ...
Page 198
... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines are all set to 1. Figure 21-16 Select 2. SAM9G45 198 “Early Read Wait State” on page 199. illustrates a chip select wait state between access on Chip Select 0 and Chip ...
Page 199
... If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See 6438G–ATARM–19-Apr-11 NRD_CYCLE Read to Write Wait State (Figure 21-17). Figure NWE_CYCLE Chip Select Wait State 21-19. SAM9G45 (Figure 199 ...
Page 200
... D[31:0] Figure 21-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] SAM9G45 200 no hold write cycle Early Read wait state no hold write cycle Early Read (READ_MODE = 0 or READ_MODE = 1) (WRITE_MODE = 0) ...