SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 125

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
FORCE_NSEQ
DMAWAIT
DRADDR
REQCLK
DRWAIT
DRSEQ
DRRD
DRCS
SEQ
CLK
CS
RD
Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses
A
T1
A
B
In cycle T1, the ARM926EJ-S initiates a sequential request to address A and the DMA
gains ownership of the TCM. DRWAIT is asserted because of DMAWAIT. The CS, A,
WE signals for the TCM are sourced from the DMA. The values of DRADDR,
DRBWL and DnRW are registered.
In cycle T2, the DMA access is still active (two cycle nonsequential access). DRWAIT
is held HIGH because of DMAWAIT.
In cycle T3, the DMA access completes and DMAWAIT is deasserted. The access
attributes captured at the end of T1 are used to generate the CS, A and WE signals for
the TCM. DRWAIT is asserted because of FORCE_NSEQ.
In cycle T4, FORCE_NSEQ is deasserted causing DRWAIT to be deasserted
indicating that the access will complete in the next cycle.
T2
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T3
A
D(B)
T4
T5
A+1
A+1
D(A)
D(A)
T6
D(A+1)
D(A+1)
A+2
A+2
T7
D(A+2)
D(A+2)
C
T8
Tightly-Coupled Memory Interface
T9
D
D
D(C)
T10
T11
D(D)
D(D)
5-17