SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 130

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Tightly-Coupled Memory Interface
5-22
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The rules for producing memory out of smaller RAM blocks are:
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Optimizing for power
Figure 5-14 on page 5-23 shows how to produce a large memory from two smaller
RAM blocks if you are optimizing for power. Separate chip select control is required
for each RAM block:
CS_bank0 = ~DRADDR[14] & DRCS
CS_bank1 = DRADDR[14] & DRCS
This ensures that only the RAM being accessed is enabled, minimizing power
consumption.
Copyright © 2001-2003 ARM Limited. All rights reserved.
If a fast design is more important than minimizing power consumption, you must
follow the example in Optimizing for speed on page 5-23.
There must be an even number of RAM blocks b (b = 2, 4, 8, for example)
Each RAM block must be the same size.
If the address width of the required memory size is n bits, the address port of the
smaller RAM blocks is m = n-(log
Address bits [m-1:0] are applied to all the RAM blocks.
Address bits [n-1:m] are gated with DRCS for a power optimized solution, or
with IRnRW for a speed optimized solution.
Pipelined address bits [n-1:m] are used to select the correct RAM read data.
b
/log
2
) bits wide.
ARM DDI0198D