SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 136

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Tightly-Coupled Memory Interface
5-28
This is similar to the previous DMA example. However, for BIST testing it is necessary
for the BIST controller to be able to force the memory chip select to both HIGH and
LOW values. This requirement means that it is necessary to hold the ARM926EJ-S core
in such a state that the internal value of the chip select is guranteed to be LOW. This can
be done by holding the ARM926EJ-S in reset (HRESETn LOW) during TCM memory
BIST testing. Note that this requires that HRESETn cannot also be used as a reset
control to the BIST controller.
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRDMAADDR[17:0]
DRADDR[17:0]
ARM926EJ-S
HRESETn
DRWD[31:0]
DRWBL[3:0]
DRDMAEN
DRDMACS
DRWAIT
DRSEQ
DRnRW
DRCS
Figure 5-19 TCM test access using BIST
1
0
1
0
1
0
BISTADDR[17:0]
BISTEN
BISTCS
BISTWD[31:0]
BISTnRW
BISTWBL[3:0]
BISTRD[31:0]
BISTRSTn
RD[31:0]
WBL[3:0]
nRW
WD[31:0]
A[17:0]
CS
ARM DDI0198D
BIST
SRAM