SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 142

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Bus Interface Unit
6.1
6-2
About the bus interface unit
The ARM926EJ-S Bus Interface Unit (BIU) arbitrates and schedules AHB requests.
The BIU contains separate masters for both instruction and data access enabling
complete AHB system flexibility. Separate masters enable multi-layer AHB (see the
Multi-layer AHB Overview) and multi-AHB systems to be implemented, giving the
benefit of increased overall bus bandwidth and a more flexible system architecture.
Each master is a fully compliant AHB bus master and implements the master functions
as defined in the AMBA Specification (Rev 2.0).
To increase system performance, write buffers are used to prevent AHB writes stalling
the ARM926EJ-S system. For more details, see Chapter 4 Caches and Write Buffer.
The data BIU AHB signals are prefixed with D, and the instruction BIU signals are
prefixed with I.
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