SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 143

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
6.2
6.2.1
6.2.2
ARM DDI0198D
Supported AHB transfers
Memory map
Transfer size
The ARM926EJ-S processor supports a subset of AHB transfers. The permitted AHB
transfers are described in:
The ARM926EJ-S processor is a cached processor with two AHB interfaces. It is a key
system design issue that the D side must be able to access the same memory as the I
side, with the same memory map. This is required not only to load code, but to enable
access to PC-relative literal pools, and for SWI and emulated instruction handlers to
work.
This is unlike some Harvard arrangements whereby the I-bus can be connected to the
ROM and the D-bus only connected to RAM/peripherals.
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four
words, or bursts of eight words. Any ARM9EJ-S core requests that are not 1, 4, or 8
words in size are split into packets of these sizes. For example, an STM of 12 words is
performed on the AHB as a burst of 8 followed by a burst of 4. If a burst is interrupted
because of either a Split or Retry response, or by removal of HGRANT, then the burst
is completed as single transfers. Consequently the ARM926EJ-S processor only uses a
subset of the possible HBURST and HSIZE encodings.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Memory map
Transfer size
Mapping of level one and level two (AHB) attributes on page 6-5
Byte and halfword accesses on page 6-6
AHB system considerations on page 6-6
AHB clocking on page 6-10.
Note
Bus Interface Unit
6-3

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