SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 144

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Bus Interface Unit
6-4
HBURST[2:0]
Single
Incr4
Incr8
Wrap8
Description
Single transfer
Four-word incrementing
burst
Eight-word incrementing
burst
Eight-word wrapping burst
Table 6-1 shows the HBURST encodings that the ARM926EJ-S processor uses, and the
operations that perform each burst size.
Incr4 and Incr8 bursts can be aligned to any word boundary.
The ARM926EJ-S processor performs all Thumb instruction fetches as word-wide
transfers on the AHB. See Mapping of level one and level two (AHB) attributes on
page 6-5.
All burst reads and writes are performed by the ARM926EJ-S processor as word-wide
transfers (HSIZE[2:0] = 010). Single reads and writes are performed as byte
(HSIZE[2:0] = 000), halfword (HSIZE[2:0] = 001), or word wide transfers
(HSIZE[2:0] = 010).
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Operation
Single transfer of word, halfword, or byte:
Half-line cache write-back. Instruction prefetch, if enabled. Four-word
burst NCNB, NCB, WT, or WB write.
Full line cache write-back. Eight-word burst NCNB, NCB, WT, or WB
write.
Cache linefill.
data write (NCNB, NCB, WT, or WB that has missed in DCache)
data read (NCNB or NCB)
NC instruction fetch (prefetched and non-prefetched)
page table walk read
continuation of a burst that either lost grant or received a
Split/Retry response.
Table 6-1 Supported HBURST encodings
ARM DDI0198D

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