SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 145

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.2.3
ARM DDI0198D
Mapping of level one and level two (AHB) attributes
Table 6-2 shows the IHPROT[3:0] and DHPROT[3:0] mappings for memory
operations.
Table walk reads that occur because of TLB misses for both data and instructions are
performed using the data side bus master. The state of DHPROT[0] can be used to
identify if a table walk is caused by an instruction fetch miss in the TLB:
DHPROT[0] = 0
DHPROT[0] = 1
Attributes specified for LDR instructions also apply for LDM, LDRD, and LDC
operations. Similarly those for STR apply for STM, STRD, and STC operations.
A DCache write-back can be caused either by an eviction during a linefill, or an explicit
cache clean operation.
Operation
DCache linefill
ICache linefill
Page table walk (data)
Page table walk (instruction)
Instruction fetch
Data access
DCache write-back
a. Priv indicates if the access was caused by a privileged (1) or User (0) access issued by the
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM9EJ-S core.
LDR/STR
STR
Indicates that an instruction fetch miss caused the page table walk.
Indicates that a data access miss caused the page table walk.
IHPROT[3:0] or
DHPROT[3:0]
{1,1,Priv
{1,1,Priv
{1,1,1,1}
{1,1,1,0}
{0,0,Priv
{0,1,Priv
{0,0,Priv
{0,1,Priv
{1,1,Priv
{1,1,1,1}
Table 6-2 IHPROT[3:0] and DHPROT[3:0] attributes
a
a
a
a
a
a
a
,1}
,0}
,0}
,0}
,1}
,1}
,1}
Description
CB, data access
CB, opcode fetch
Page table walk caused by a TLB miss
for a data access
Page table walk caused by a TLB miss
for an instruction fetch
NCNB opcode fetch
NCB opcode fetch
NCNB
NCB
WT/WB
-
Bus Interface Unit
6-5